Skip to content
GitLab
Explore
Sign in
Projects
Hdlmake
Repository
hdl-make
hdlmake
dep_file.py
Find file
Blame
History
Permalink
Create the MODULE relation in Verilog and identify it with ARCHITECTURE in VHDL
· 43e115fc
Javier D. Garcia-Lasheras
authored
May 31, 2016
43e115fc