... | ... | @@ -44,8 +44,9 @@ PCI express bursts are divided in single reads and writes. |
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Data are coming from the packet decoder. Wishbone signals are generated
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and the master waits for an acknowledge. The incoming requests are saved
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in a FIFO. Javier: Please explain what happens in case of FIFO overflow,
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and how deep is the FIFO.
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in a FIFO. The FIFO depth is 16. The Wishbone master is allowing the
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GN4124 chip to send a request only if the FIFO is empty. The latency of
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the ready signal of the Wishbone master implies this FIFO.
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## Arbiter
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