... | ... | @@ -4,7 +4,7 @@ First draft for GN4124 core technical specification. |
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## Introduction
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This specification describes how the core work internally. For each
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This specification describes how the core works internally. For each
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internal block, we give a summary description of its
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function.
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... | ... | @@ -40,11 +40,12 @@ like: |
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The Wishbone master implements a master for the Wishbone interconnection
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bus. It transforms a PCIe write into a Wishbone write and a PCIe read
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into a Wishbone read. Only single word reads and writes are supported.
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PCI express burst are divided in sigle reads and writes.
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PCI express bursts are divided in sigle reads and writes.
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Data are coming from the packet decoder. Wishbone signals are generated
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and the master waits for an acknowledge. The incoming requests are saved
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in a FIFO.
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in a FIFO. Javier: Please explain what happens in case of FIFO overflow,
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and how deep is the FIFO.
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## Arbiter
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