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![](/uploads/e1ac973d81801d37c00cb46c666addd3/GN4124core_arch.png)
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## De-multiplexer
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This block takes the double data rate 16-bit P2L (PCI Express to Local
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Bus direction) bus from the GN4124 device and converts it to a single
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data rate 32-bit bus for use inside the GN4124 core.
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## Multiplexer
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It takes the internal single data rate 32 bit data and transmits it as
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double data rate 16-bit data on the L2P (Local Bus to PCI Express
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direction) bus.
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## Packet decoder
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This block extracts header information, address, data, byte enables, and
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timing controls of the packets from the GN4124 chip. It provides signals
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like :
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- type of packet (target read request, target write request,master
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read completion ...)
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- Begin of packet
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- Address that will increment with data
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- Data
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- End of packet
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## Wishbone master
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The Wishbone master implements a master for the Wishbone interconnection
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bus. It transforms a PCIe write into a Wishbone write and a PCIe read
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into a Wishbone read. Only single word reads and writes are supported.
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PCI express burst are divided in sigle reads and writes.
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Data are coming from the packet decoder. Wishbone signals are generated
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and the master waits for an acknowledge. The incoming requests are saved
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in a FIFO.
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## Arbiter
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Arbitrate between Wishbone master, DMA master and DMA
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sequencer
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## DMA controller
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![](/uploads/72475e9ec5b39a777d6899ce26e7e4fe/GN4124core_sequencer.png)
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## DMA master
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## Interrupt clock bridge
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It transforms input interrupt one-tick-long pulse clocked by sys\_clk\_i
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in a one-tick-long pulse clocked by the GN4124 local bus clock.
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### Files
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