... | ... | @@ -48,8 +48,13 @@ in a FIFO. |
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## Arbiter
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Arbitrate between Wishbone master, DMA master and DMA
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sequencer
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Arbitrate between Wishbone master, DMA master and DMA sequencer. The
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arbiter is waiting for a request signal from one of this blocks and it
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grants the bus to the first requester until the end of the packet.
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The highest priority is for Wishbone master and the lower priority is
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for the DMA
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controler.
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## DMA controller
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... | ... | |