... | ... | @@ -46,7 +46,8 @@ Data are coming from the packet decoder. Wishbone signals are generated |
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and the master waits for an acknowledge. The incoming requests are saved
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in a FIFO. The FIFO depth is 16. The Wishbone master is allowing the
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GN4124 chip to send a request only if the FIFO is empty. The latency of
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the ready signal of the Wishbone master implies this FIFO.
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the transfer between the GN4124 chip and the Wishbone master makes this
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FIFO necessary
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## Arbiter
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