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# GN4124 core - Release 2.0
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-----
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## Sources
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- "HDL sources":
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-----
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## Entity changes
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- Additional generic, to set the ACk wait timeout (in wishbone clock
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cycles).
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- g\_ACK\_TIMEOUT
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- Additional ports
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- csr\_err\_i, used to terminate the wishbone cycle if asserted.
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- csr\_rty\_i, not used. Reserved for future use.
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- csr\_int\_i, not used. Reserved for future use.
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- dma\_err\_i, not used. Reserved for future use.
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- dma\_rty\_i, not used. Reserved for future use.
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- dma\_int\_i, not used. Reserved for future use.
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-----
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## Release date
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- 01 March 2014
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-----
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04 February 2014
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