inferred_async_fifo_dual_reset : spurious pulse on almost_full_int after reset

my instanciation if anybody wants to reproduce:

  fifo : ENTITY work.generic_async_fifo_dual_rst
    GENERIC MAP(
      g_data_width                 => 74,
      g_size                       => g_size,
      g_show_ahead                 => TRUE,
      g_with_rd_empty              => true,
      g_with_rd_full               => false,
      g_with_rd_almost_empty       => false,
      g_with_rd_almost_full        => true,
      g_with_rd_count              => true,
      g_with_wr_empty              => false,
      g_with_wr_full               => true,
      g_with_wr_almost_empty       => false,
      g_with_wr_almost_full        => false,
      g_with_wr_count              => false,
      g_almost_empty_threshold     => 0,
      g_almost_full_threshold      => g_size - 2,
      g_memory_implementation_hint => "auto"
    )

almost_full_int (and so wr_almost_full_o & rd_almost_full_o) will pulse out of reset because wr_count reg is undef for the first clock cycle out of reset in sim:

and adding a reset statement for wr_count fixes it when added here: https://ohwr.org/project/general-cores/blob/master/modules/genrams/common/inferred_async_fifo_dual_rst.vhd#L284

vivado 2022.2.2, xsim

will do a PR later