Several small changes suggestion
Hi,
as I was using this repository for last few weeks in one of our project,
I've made several small changes/updates to the repository. Please find
attached an archive with all these changes:
- added default values for determined start-up state
- added assignments to (new) unspecified WB signals
- removed synchronous reset from sensitivity lists
- added ASYNC_REG attribute for better timing analysis/simulation in Xilinx tools
- added default values; typos
- propagated CDR_N/O generics up the hierarchy; added assignments to (new) unspecified WB signals
- added copy of original documentation for wb_spi and wb_onewire_master
If any of these changes is meaningful enough, please use it for a future release.
With all the best,
Jan