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FSI Data Acquisition Path Gateware and Software
Commit a790d75b authored by Tristan Gingold's avatar Tristan Gingold Committed by Maciej Lipinski
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tentatively remove bufg before pll

parent 2811b47f
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Showing with 1 addition and 11 deletions
hdl/rtl/sys/diot_sys_top.vhd
View file @ a790d75b
......@@ -333,7 +333,6 @@ begin
signal rst : std_logic;
signal clk_100m_oserdes_int, clk_400m_oserdes_int : std_logic_vector(3 downto 1);
signal fpga_pl_clkref_bufg : std_logic;
-- Ready lines for each idelayctrl (replicated).
signal dly_rdy : std_logic_vector(41 downto 0);
......@@ -345,13 +344,6 @@ begin
IB => fpga_pl_clkref_n_i
);
inst_bufg_fpga_pl : BUFG
port map (
O => fpga_pl_clkref_bufg, -- 1-bit output: Buffer
I => fpga_pl_clkref -- 1-bit input: Buffer
);
inst_PLLE4_BASE : PLLE4_BASE
generic map (
CLKFBOUT_MULT => 12,
......@@ -381,7 +373,7 @@ begin
CLKOUTPHY => open,
LOCKED => clk_locked,
CLKFBIN => clk_buffb,
CLKIN => fpga_pl_clkref_bufg,
CLKIN => fpga_pl_clkref,
CLKOUTPHYEN => '0',
PWRDWN => '0',
RST => pl_reset
......
hdl/syn/diot_sys_top/diot_sys_top.xdc
View file @ a790d75b
......@@ -565,6 +565,4 @@ set_property LOC BITSLICE_CONTROL_X0Y35 [get_cells blk_clock.gen_idelayctrl[41].
# set_clock_groups -asynchronous -group [get_clocks *helper*] -group [get_clocks *clk_main*] -group [get_clocks *clk_sfp*] -group [get_clocks *clk_rx*] -group [get_clocks clk_tx]
set_property LOC PLL_X1Y7 [get_cells blk_clock.inst_PLLE4_BASE]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets fpga_pl_clkref_bufg]
set_property DONT_TOUCH TRUE [get_cells {blk_clock.gen_bufg_oserdes[*].inst_bufgdiv_clk400m_oserdes}]
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