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FSI Data Acquisition Path Gateware and Software
Commit 815a0f73 authored by Maciej Lipinski's avatar Maciej Lipinski
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port previous commit to diot sys acq ip

parent 6a8c3f3b
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hdl/rtl/sys/diot_sys_acq_ip.vhd
View file @ 815a0f73
......@@ -173,6 +173,9 @@ begin
signal clk_buffb : std_logic;
signal clk_300m_int : std_logic;
signal clk_400m_int : std_logic;
signal clk_100m_int : std_logic;
signal clk_400m_oserdes_int : std_logic;
signal clk_100m_oserdes_int : std_logic;
signal clk_locked : std_logic;
signal pl_reset : std_logic;
signal rst_cnt : unsigned (3 downto 0);
......@@ -194,41 +197,64 @@ begin
IB => fpga_pl_clkref_n_i
);
inst_PLLE4_BASE : PLLE4_BASE
inst_MMCME3_BASE : MMCME3_BASE
generic map (
CLKFBOUT_MULT => 12,
CLKFBOUT_PHASE => 0.0,
CLKIN_PERIOD => 10.0,
CLKOUT0_DIVIDE => 3,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 4,
BANDWIDTH => "OPTIMIZED", -- Jitter programming (HIGH, LOW, OPTIMIZED)
CLKFBOUT_MULT_F => 12.0, -- Multiply value for all CLKOUT (2.000-64.000)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000)
CLKIN1_PERIOD => 10.0, -- Input clock period in ns units, ps resolution (i.e., 33.333 is 30 MHz).
CLKOUT0_DIVIDE_F => 3.0, -- Divide amount for CLKOUT0 (1.000-128.000)
CLKOUT0_DUTY_CYCLE => 0.5,-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.0,-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT1_PHASE => 0.0,
CLKOUTPHY_MODE => "VCO",
DIVCLK_DIVIDE => 1,
IS_CLKFBIN_INVERTED => '0',
IS_CLKIN_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER => 0.01,
STARTUP_WAIT => "FALSE"
)
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
CLKOUT1_DIVIDE => 4, -- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT2_DIVIDE => 12,
CLKOUT3_DIVIDE => 3,
CLKOUT4_DIVIDE => 12,
CLKOUT5_DIVIDE => 12,
CLKOUT6_DIVIDE => 12,
CLKOUT4_CASCADE => "FALSE", -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
DIVCLK_DIVIDE => 1, -- Master division value (1-106)
IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
IS_CLKIN1_INVERTED => '0', -- Optional inversion for CLKIN1
IS_PWRDWN_INVERTED => '0', -- Optional inversion for PWRDWN
IS_RST_INVERTED => '0', -- Optional inversion for RST
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999)
STARTUP_WAIT => "FALSE" -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
CLKFBOUT => clk_fb,
CLKOUT0 => clk_400m_int,
CLKOUT0B => open,
CLKOUT1 => clk_300m_int,
CLKOUT1B => open,
CLKOUTPHY => open,
LOCKED => clk_locked,
CLKFBIN => clk_buffb,
CLKIN => fpga_pl_clkref,
CLKOUTPHYEN => '0',
PWRDWN => '0',
RST => pl_reset
CLKOUT0 => clk_400m_int, -- 1-bit output: CLKOUT0
CLKOUT0B => open, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => clk_300m_int, -- 1-bit output: CLKOUT1
CLKOUT1B => open, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => clk_100m_int, -- 1-bit output: CLKOUT2
CLKOUT2B => open, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => clk_400m_oserdes_int, -- 1-bit output: CLKOUT3
CLKOUT3B => open, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => clk_100m_oserdes_int, -- 1-bit output: CLKOUT4
CLKOUT5 => open, -- 1-bit output: CLKOUT5
CLKOUT6 => open, -- 1-bit output: CLKOUT6
CLKFBOUT => clk_fb, -- 1-bit output: Feedback clock
CLKFBOUTB => open, -- 1-bit output: Inverted CLKFBOUT
LOCKED => clk_locked, -- 1-bit output: LOCK
CLKIN1 => fpga_pl_clkref, -- 1-bit input: Clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => pl_reset, -- 1-bit input: Reset
CLKFBIN => clk_buffb -- 1-bit input: Feedback clock
);
led0_o <= clk_locked;
pl_reset <= not pl_reset_n;
......@@ -260,70 +286,37 @@ begin
O => clk_buffb
);
inst_bufg_clk100m : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 4,
IS_CE_INVERTED => '0', -- Optional inversion for CE
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
IS_I_INVERTED => '0' -- Optional inversion for I
)
inst_bufg_clk100m : BUFG
port map (
O => clk_100m, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => clk_400m_int -- 1-bit input: Buffer
I => clk_100m_int -- 1-bit input: Buffer
);
inst_bufg_clk100m_oserdes : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 4,
IS_CE_INVERTED => '0', -- Optional inversion for CE
IS_CLR_INVERTED => '0', -- Optional inversion for CLR
IS_I_INVERTED => '0' -- Optional inversion for I
)
port map (
O => clk_100m_oserdes, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => clk_400m_int -- 1-bit input: Buffer
);
inst_bufg_300m: BUFG
port map (
I => clk_300m_int,
O => clk_300m
);
-- Also use a bufgce_div for clk_400m to reduce (TBC) the skew between
-- clk_400m and clk_100m
inst_bufgdiv_clk400m : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 1,
IS_CE_INVERTED => '0',
IS_CLR_INVERTED => '0',
IS_I_INVERTED => '0'
)
inst_bufg_clk400m : BUFG
port map (
O => clk_400m, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => clk_400m_int -- 1-bit input: Buffer
);
);
inst_bufg_clk100m_oserdes : BUFG
port map (
O => clk_100m_oserdes, -- 1-bit output: Buffer
I => clk_100m_oserdes_int -- 1-bit input: Buffer
);
inst_bufgdiv_clk400m_oserdes : BUFGCE_DIV
generic map (
BUFGCE_DIVIDE => 1,
IS_CE_INVERTED => '0',
IS_CLR_INVERTED => '0',
IS_I_INVERTED => '0'
)
inst_bufg_clk400m_oserdes : BUFG
port map (
O => clk_400m_oserdes, -- 1-bit output: Buffer
CE => '1', -- 1-bit input: Buffer enable
CLR => '0', -- 1-bit input: Asynchronous clear
I => clk_400m_int -- 1-bit input: Buffer
I => clk_400m_oserdes_int -- 1-bit input: Buffer
);
process (pl_reset_n, clk_locked, clk_100m)
begin
if pl_reset_n = '0' or clk_locked = '0' then
......
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