sys: change patterns, also resync serdes

2f78019e · Tristan Gingold · 46a5100e · 2f78019e · 2f78019e · 2f78019e
Commit 2f78019e authored Sep 23, 2021 by Tristan Gingold
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Showing with 13 additions and 7 deletions

diot_sys_patterns.vhd hdl/rtl/sys/diot_sys_patterns.vhd +7 -5

sys_fsi_core.vhd hdl/rtl/sys/sys_fsi_core.vhd +1 -0

sys_fsi_rx.vhd hdl/rtl/sys/sys_fsi_rx.vhd +5 -2

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--- a/hdl/rtl/sys/diot_sys_patterns.vhd
+++ b/hdl/rtl/sys/diot_sys_patterns.vhd
@@ -27,6 +27,7 @@ architecture arch of diot_sys_patterns is
 begin
  process (clk_100m_i)
    variable patcnt : unsigned (11 downto 0);
+    variable sl : unsigned(3 downto 0);
  begin
    if rising_edge(clk_100m_i) then
      if rst_100m_n_i = '0' then
@@ -37,12 +38,13 @@ begin
        end if;
        for i in samples_o'range loop
          for j in 0 to 7 loop
-            samples_o (i)(j) <= std_logic_vector
-              (patcnt (7 downto 0) & to_unsigned (j + i*8, 4));
+            sl := to_unsigned(j + 1, 4);
+            samples_o (i)(j) <= std_logic_vector (sl & sl & sl);
+--              (patcnt (7 downto 0) & to_unsigned (j + i*8, 4));
          end loop;
-          samples_o (i)(7) <= std_logic_vector (patcnt);
-          samples_o (i)(6) <=
-            std_logic_vector (to_unsigned (6 + i*8, 8) & "0000");
+--          samples_o (i)(7) <= std_logic_vector (patcnt);
+--          samples_o (i)(6) <=
+--            std_logic_vector (to_unsigned (6 + i*8, 8) & "0000");
        end loop;
      end if;
    end if;

--- a/hdl/rtl/sys/sys_fsi_core.vhd
+++ b/hdl/rtl/sys/sys_fsi_core.vhd
@@ -130,6 +130,7 @@ begin
        dat_o => samples (i),
        locking_i => lock,
        locked_o => locked (i),
+        resync_i => resync_i,
        freeze_delays_i => freeze_delays_i,
        stat_sel_ch_i => stat_sel_ch_i,
        stat_sel_dl_i => stat_sel_dl_i,

--- a/hdl/rtl/sys/sys_fsi_rx.vhd
+++ b/hdl/rtl/sys/sys_fsi_rx.vhd
@@ -27,6 +27,9 @@ entity sys_fsi_rx is
    --  Locking status
    locked_o : out std_logic;

+    --  Resync serdes
+    resync_i : std_logic;
+
    --  Do not change delays when set.
    freeze_delays_i : std_logic;

@@ -315,7 +318,7 @@ begin
    process (clk_100m_i) is
    begin
      if rising_edge(clk_100m_i) then
-        if rst_n_i = '0' then
+        if rst_n_i = '0' or resync_i = '1' then
          cntvalue <= to_unsigned(250, 9);
          dly <= (others => '1');
          load <= '0';
@@ -412,7 +415,7 @@ begin
    process (clk_100m_i) is
    begin
      if rising_edge(clk_100m_i) then
-        if rst_n_i = '0' then
+        if rst_n_i = '0' or resync_i = '1' then
          locked (i) <= '0';
          lock_cnt <= 0;
          bitslip_cnt <= (others => '0');