diot_sys_top: insert a bufg before the bufgce_div

1028f2aa · Tristan Gingold · Maciej Lipinski · 173261ac · 1028f2aa
Commit 1028f2aa authored Dec 01, 2021 by Tristan Gingold Committed by Maciej Lipinski Dec 02, 2021
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Showing with 9 additions and 2 deletions

diot_sys_top.vhd hdl/rtl/sys/diot_sys_top.vhd +9 -2

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--- a/hdl/rtl/sys/diot_sys_top.vhd
+++ b/hdl/rtl/sys/diot_sys_top.vhd
@@ -332,6 +332,7 @@ begin
    signal rst_cnt : unsigned (3 downto 0);
    signal rst : std_logic;

+    signal clk_400m_oserdes_bufg : std_logic;
    signal clk_100m_oserdes_int, clk_400m_oserdes_int : std_logic_vector(5 downto 1);

    --  Ready lines for each idelayctrl (replicated).
@@ -446,6 +447,12 @@ begin
        I => clk_400m_int      -- 1-bit input: Buffer
     );

+    inst_bufg_oserdes: BUFG
+      port map (
+        I => clk_400m_int,
+        O => clk_400m_oserdes_bufg
+      );
+
    gen_bufg_oserdes: for i in clk_100m_oserdes_int'range generate
      inst_bufg_clk100m_oserdes : BUFGCE_DIV
        generic map (
@@ -458,7 +465,7 @@ begin
          O => clk_100m_oserdes_int(i),  -- 1-bit output: Buffer
          CE => '1',             -- 1-bit input: Buffer enable
          CLR => '0',            -- 1-bit input: Asynchronous clear
-          I => clk_400m_int      -- 1-bit input: Buffer
+          I => clk_400m_oserdes_bufg      -- 1-bit input: Buffer
       );

      inst_bufgdiv_clk400m_oserdes : BUFGCE_DIV
@@ -472,7 +479,7 @@ begin
          O => clk_400m_oserdes_int(i), -- 1-bit output: Buffer
          CE => '1',             -- 1-bit input: Buffer enable
          CLR => '0',            -- 1-bit input: Asynchronous clear
-          I => clk_400m_int      -- 1-bit input: Buffer
+          I => clk_400m_oserdes_bufg      -- 1-bit input: Buffer
       );
    end generate;