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FSI Data Acquisition Path Gateware and Software
Commit 0baec4c9 authored by Tristan Gingold's avatar Tristan Gingold Committed by Maciej Lipinski
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diot_sys_top: set additional constraint

parent 3385f559
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hdl/syn/diot_sys_top/diot_sys_top.xdc
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......@@ -566,3 +566,4 @@ set_property LOC BITSLICE_CONTROL_X0Y35 [get_cells blk_clock.gen_idelayctrl[41].
set_property LOC PLL_X1Y3 [get_cells blk_clock.inst_PLLE4_BASE]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets fpga_pl_clkref_bufg]
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