A few modifications to improve clarity

- A diagram of an example case to ilustrate abstract concepts - Going to UK English (CERN-standard) - Bumping patch level to 1 - Adding an option to easily reference figure numbers from text - An explanation of what happens at host boot time in the example - Rephrasing in a few places for clarity

A few modifications to improve clarity
- A diagram of an example case to ilustrate abstract concepts - Going to UK English (CERN-standard) - Bumping patch level to 1 - Adding an option to easily reference figure numbers from text - An explanation of what happens at host boot time in the example - Rephrasing in a few places for clarity
b8d32d74 · Javier Serrano · 990fb9cc · b8d32d74 · b8d32d74 · b8d32d74
Commit b8d32d74 authored Apr 24, 2020 by Javier Serrano
6 changed files
--- a/conf.py
+++ b/conf.py
@@ -26,7 +26,7 @@ author = 'Federico Vaga'
 # The short X.Y version
 version = '1.0'
 # The full version, including alpha/beta/rc tags
-release = '1.0.0'
+release = '1.0.1'


 # -- General configuration ---------------------------------------------------
@@ -153,3 +153,7 @@ texinfo_documents = [
     author, 'FPGAInterfaceDesign', 'One line description of project.',
     'Miscellaneous'),
 ]
+
+# -- Options for figure numbering  -------------------------------------------
+
+numfig = True
--- a/device-structure.rst
+++ b/device-structure.rst
--- a/figures/spec_diagram.drawio
+++ b/figures/spec_diagram.drawio
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\ No newline at end of file
--- a/figures/spec_diagram.png
+++ b/figures/spec_diagram.png
--- a/figures/spec_diagram.svg
+++ b/figures/spec_diagram.svg
--- a/index.rst
+++ b/index.rst
@@ -2,14 +2,17 @@
 FPGA Device Identification
 ==========================

-The purpose of this document is to aide HDL developers in designing FPGA
-applications so that the exported interface can be easily used by the
-correspondent low-level software.
+The purpose of this document is to help HDL designers in the development of FPGA
+designs so that the exported interface can be easily used by the corresponding
+low-level software.

-This document is tailored around the CERN BE-CO-HT needs to handle different
-FPGA applications on SVEC, SPEC and similar FMC carrier boards.
+This document is tailored to the needs of the BE-CO-HT section at CERN to handle
+different FPGA designs on the SVEC_, SPEC_ and similar FMC carrier boards.

 .. toctree::
   :maxdepth: 1

   device-structure
+
+.. _SVEC: https://www.ohwr.org/project/svec/wikis
+.. _SPEC: https://www.ohwr.org/project/spec/wikis