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Commit a9463ff5 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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Removed HDL implementation -- it is now part of general-cores (and more up-to-date there).

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hdl/altera_pcie.qip deleted 100644 → 0
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hdl/altera_pcie.sdc deleted 100644 → 0
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# The refclk assignment may need to be renamed to match design top level port name.
# May be desireable to move refclk assignment to a top level SDC file.
#create_clock -period "100 MHz" -name {refclk} {refclk}
#create_clock -period "100 MHz" -name {fixedclk_serdes} {fixedclk_serdes}
# testin bits are either static or treated asynchronously, cut the paths.
#set_false_path -to [get_pins -hierarchical {*hssi_pcie_hip|testin[*]} ]
# SERDES Digital Reset inputs are asynchronous
#set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
#set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
#
# The following multicycle path constraints are only valid if the logic use to sample the tl_cfg_ctl and tl_cfg_sts signals
# are as designed in the Altera provided files altpcierd_tl_cfg_sample.v and altpcierd_tl_cfg_sample.vhd
#
# These constraints are only valid when the altpcierd_tl_cfg_sample module or entity is used with the PCI Express
# Hard IP block in Stratix IV, Arria II, Cyclone IV and HardCopy IV devices.
# These constraints are not neccesary for PCI Express Hard IP in Stratix V devices.
#
#global tl_cfg_ctl_wr_setup
#global tl_cfg_sts_wr_setup
#
# If there are consistent hold time violations for the tl_cfg_ctl_wr signal in your chosen device and design,
# the multicycle setup constraint for tl_cfg_ctl_wr can be changed from 1 to 0 in the following variable:
#set tl_cfg_ctl_wr_setup 1
#
# If there are consistent hold time violations for the tl_cfg_sts_wr signal in your chosen device and design,
# the multicycle setup constraint for tl_cfg_sts_wr can be changed from 1 to 0 in the following variable:
#set tl_cfg_sts_wr_setup 1
#
#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr}] $tl_cfg_ctl_wr_setup
#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] [expr $tl_cfg_ctl_wr_setup + 2]
#set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] 3
#
#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr}] $tl_cfg_sts_wr_setup
#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts[*]}] [expr $tl_cfg_sts_wr_setup + 2]
#set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts[*]}] 3
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hdl/altera_pcie_core.vhd deleted 100644 → 0
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hdl/altera_pcie_pll.qip deleted 100644 → 0
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie_pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_pcie_pll.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_pcie_pll.ppf"]
hdl/altera_pcie_pll.vhd deleted 100644 → 0
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set_global_assignment -name IP_TOOL_NAME "ALTGX_RECONFIG"
set_global_assignment -name IP_TOOL_VERSION "11.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_reconfig.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_reconfig.cmp"]
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hdl/ip_compiler_for_pci_express-library/altpcie_pclk_align.v deleted 100644 → 0
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//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Logic Core: PCI Express Megacore Function
// Company: Altera Corporation.
// www.altera.com
// Author: IPBU SIO Group
//
// Description: Altera PCI Express MegaCore function clk phase alignment
// module for S4GX ES silicon
//
// Copyright 2009 Altera Corporation. All rights reserved. This source code
// is highly confidential and proprietary information of Altera and is being
// provided in accordance with and subject to the protections of a
// Non-Disclosure Agreement which governs its use and disclosure. Altera
// products and services are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws. Altera
// assumes no responsibility or liability arising out of the application or use
// of this source code.
//
// For Best Viewing Set tab stops to 4 spaces.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module altpcie_pclk_align
(
rst,
clock,
offset,
onestep,
onestep_dir,
PCLK_Master,
PCLK_Slave,
PhaseUpDown,
PhaseStep,
PhaseDone,
AlignLock,
PhaseDone_reg,
compout_reg,
pcie_sw_in,
pcie_sw_out
);
input rst;
input clock;
input [7:0] offset;
input onestep;
input onestep_dir;
input PCLK_Master;
input PCLK_Slave;
input PhaseDone;
output PhaseUpDown;
output PhaseStep;
output AlignLock;
output PhaseDone_reg;
output compout_reg;
input pcie_sw_in;
output pcie_sw_out;
reg PhaseUpDown;
reg PhaseStep;
reg AlignLock;
wire PhaseDone_reg = 0;
wire compout_reg = 0;
localparam DREG_SIZE = 128;
localparam BIAS_ONE = 1;
reg [3:0] align_sm;
localparam INIT = 0;
localparam EVAL = 1;
localparam ADVC = 2;
localparam DELY = 3;
localparam BACK = 4;
localparam ERR = 5;
localparam DONE = 6;
localparam MNUL = 7;
// debug txt
reg [4 * 8 -1 :0] align_sm_txt;
always@(align_sm)
case(align_sm)
INIT: align_sm_txt = "init";
EVAL: align_sm_txt = "eval";
ADVC: align_sm_txt = "advc";
DELY: align_sm_txt = "dely";
BACK: align_sm_txt = "back";
ERR: align_sm_txt = "err";
DONE: align_sm_txt = "done";
MNUL: align_sm_txt = "mnul";
endcase
reg [DREG_SIZE-1: 0] delay_reg;
integer i;
reg all_zero;
reg all_one;
reg chk_req;
wire chk_ack;
reg [7:0] chk_cnt;
reg chk_ack_r;
reg chk_ack_rr;
reg chk_ok;
// controls
reg found_zero; // found all zeros
reg found_meta; // found metastable region
reg found_one; // found all ones
reg [7:0] window_cnt; // count the number of taps between all zero and all ones
reg clr_window_cnt;
reg inc_window_cnt;
reg dec_window_cnt;
reg half_window_cnt;
reg [1:0] retrain_cnt;
reg pcie_sw_r;
reg pcie_sw_rr;
reg pcie_sw_out;
assign chk_ack = chk_cnt[7];
always @ (posedge PCLK_Master or posedge rst)
begin
if (rst)
begin
delay_reg <= {DREG_SIZE{1'b0}};
all_zero <= 1'b1;
all_one <= 1'b0;
chk_cnt <= 0;
end
else
begin
delay_reg[0] <= PCLK_Slave;
for (i = 1; i < DREG_SIZE; i = i + 1)
delay_reg[i] <= delay_reg[i-1];
// discount the first two flops which are sync flops
if (chk_cnt == 8'h80)
begin
all_zero <= ~|delay_reg[DREG_SIZE-1:2];
all_one <= &delay_reg[DREG_SIZE-1:2];
end
// handshake with slow clock
if (chk_req & (chk_cnt == 8'h8f))
chk_cnt <= 0;
else if (chk_cnt == 8'h8f)
chk_cnt <= chk_cnt;
else
chk_cnt <= chk_cnt + 1;
end
end
always @ (posedge clock or posedge rst)
begin
if (rst)
begin
align_sm <= INIT;
chk_req <= 0;
chk_ack_r <= 0;
chk_ack_rr <= 0;
chk_ok <= 0;
found_zero <= 0;
found_meta <= 0;
found_one <= 0;
PhaseUpDown <= 0;
PhaseStep <= 0;
window_cnt <= 8'h00;
clr_window_cnt <= 0;
inc_window_cnt <= 0;
dec_window_cnt <= 0;
half_window_cnt <= 0;
AlignLock <= 0;
retrain_cnt <= 0;
end
else
begin
chk_ack_r <= chk_ack;
chk_ack_rr <= chk_ack_r;
if ((chk_ack_rr == 0) & (chk_ack_r == 1))
chk_ok <= 1;
else
chk_ok <= 0;
if (align_sm == DONE)
AlignLock <= 1'b1;
if (clr_window_cnt)
window_cnt <= offset;
else if (window_cnt == 8'hff)
window_cnt <= window_cnt;
else if (inc_window_cnt)
window_cnt <= window_cnt + 1;
else if (dec_window_cnt & (window_cnt > 0))
window_cnt <= window_cnt - 1;
else if (half_window_cnt)
window_cnt <= {1'b0,window_cnt[7:1]};
// limit the number of retrains
if (retrain_cnt == 2'b11)
retrain_cnt <= retrain_cnt;
else if (align_sm == ERR)
retrain_cnt <= retrain_cnt + 1;
case (align_sm)
INIT:
begin
chk_req <= 1;
align_sm <= EVAL;
clr_window_cnt <= 1;
found_zero <= 0;
found_meta <= 0;
found_one <= 0;
end
EVAL:
if (chk_ok)
begin
chk_req <= 0;
clr_window_cnt <= 0;
casex ({found_zero,found_meta,found_one})
3'b000 : // init case
begin
if (all_zero)
begin
found_zero <= 1;
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
end
else if (all_one)
begin
found_one <= 1;
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
end
else
begin
found_meta <= 1;
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
end
end
3'b010 : // metasable, delay till get all zero
begin
if (all_zero)
begin
found_zero <= 1;
PhaseUpDown <= 0;
PhaseStep <= 0;
align_sm <= INIT;
inc_window_cnt <= 0;
end
else
begin
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
end
end
3'b110 : // look for all one and compute window
begin
if (all_one)
begin
found_one <= 1;
PhaseStep <= 1;
align_sm <= BACK;
if (BIAS_ONE)
begin
clr_window_cnt <= 1;
PhaseUpDown <= 0;
end
else
begin
PhaseUpDown <= 1;
half_window_cnt <= 1;
end
end
else
begin
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
inc_window_cnt <= 1;
end
end
3'b100 : // keep advancing to look for metasable phase
begin
PhaseUpDown <= 0;
PhaseStep <= 1;
align_sm <= ADVC;
if (all_zero == 0) // got either metsable or ones and found the window edge
begin
found_meta <= 1;
inc_window_cnt <= 1;
end
end
3'b001 : // keep delaying to look for metasable phase
begin
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
if (all_one == 0) // got either metsable or ones and found the window edge
begin
found_meta <= 1;
inc_window_cnt <= 1;
end
end
3'b011 : // look for all zero and compute window
begin
if (all_zero)
begin
found_zero <= 1;
PhaseStep <= 0;
PhaseUpDown <= 0;
align_sm <= INIT;
if (BIAS_ONE == 0) // if bias to one, go back all the way
half_window_cnt <= 1;
else
inc_window_cnt <= 1;
end
else
begin
PhaseUpDown <= 1;
PhaseStep <= 1;
align_sm <= DELY;
inc_window_cnt <= 1;
end
end
3'b111 : // middling the setup hold window
begin
if (window_cnt > 0)
begin
PhaseStep <= 1;
align_sm <= BACK;
dec_window_cnt <= 1;
end
else
align_sm <= DONE;
end
3'b101 : // error case should never happen
begin
align_sm <= ERR;
clr_window_cnt <= 1;
found_zero <= 0;
found_one <= 0;
found_meta <= 0;
end
endcase
end
ADVC:
begin
inc_window_cnt <= 0;
if (PhaseDone == 0)
begin
PhaseStep <= 0;
chk_req <= 1;
align_sm <= EVAL;
end
end
DELY:
begin
inc_window_cnt <= 0;
if (PhaseDone == 0)
begin
PhaseStep <= 0;
chk_req <= 1;
align_sm <= EVAL;
end
end
BACK:
begin
half_window_cnt <= 0;
dec_window_cnt <= 0;
inc_window_cnt <= 0;
clr_window_cnt <= 0;
if (PhaseDone == 0)
begin
PhaseStep <= 0;
chk_req <= 1;
align_sm <= EVAL;
end
end
DONE:
begin
if (chk_ok)
chk_req <= 0;
if (onestep) // manual adjust
begin
align_sm <= MNUL;
PhaseStep <= 1;
PhaseUpDown <= onestep_dir;
end
end
MNUL:
if (PhaseDone == 0)
begin
PhaseStep <= 0;
chk_req <= 1;
align_sm <= DONE;
end
ERR:
begin
clr_window_cnt <= 0;
align_sm <= INIT;
end
default:
align_sm <= INIT;
endcase
end
end
// synchronization for pcie_sw
always @ (posedge PCLK_Master or posedge rst)
begin
if (rst)
begin
pcie_sw_r <= 0;
pcie_sw_rr <= 0;
pcie_sw_out <= 0;
end
else
begin
pcie_sw_r <= pcie_sw_in;
pcie_sw_rr <= pcie_sw_r;
pcie_sw_out <= pcie_sw_rr;
end
end
endmodule
hdl/ip_compiler_for_pci_express-library/altpcie_phasefifo.v deleted 100644 → 0
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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : PCI Express Reference Design Example Application
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcie_phasefifo.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This module allows data to pass between two clock domains where the
// frequency is identical but with different phase offset
//-----------------------------------------------------------------------------
// Copyright (c) 2008 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcie_phasefifo (
npor,
wclk,
wdata,
rclk,
rdata
);
parameter DATA_SIZE = 20;
parameter DDR_MODE = 0;
input npor;
input wclk;
input[DATA_SIZE - 1:0] wdata;
input rclk;
output [DATA_SIZE - 1:0] rdata;
wire [DATA_SIZE - 1:0] rdata;
reg rerror;
reg[3-DDR_MODE:0] waddr;
reg[3:0] raddr;
reg strobe_r;
reg strobe_rr;
reg npor_rd_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg npor_rd_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg npor_wr_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg npor_wr_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
altsyncram #(
.intended_device_family ( "Stratix GX"),
.operation_mode ( "DUAL_PORT"),
.width_a (DATA_SIZE),
.widthad_a (4-DDR_MODE),
.numwords_a (2**(4-DDR_MODE)),
.width_b (DATA_SIZE / (DDR_MODE + 1)),
.widthad_b (4),
.numwords_b (16),
.lpm_type ( "altsyncram"),
.width_byteena_a ( 1),
.outdata_reg_b ( "CLOCK1"),
.indata_aclr_a ( "NONE"),
.wrcontrol_aclr_a ( "NONE"),
.address_aclr_a ( "NONE"),
.address_reg_b ( "CLOCK1"),
.address_aclr_b ( "NONE"),
.outdata_aclr_b ( "NONE"),
.ram_block_type ( "AUTO")
) altsyncram_component(
.wren_a(1'b1),
.wren_b(1'b0),
.rden_b(1'b1),
.data_a(wdata),
.data_b({(DATA_SIZE / (DDR_MODE + 1)){1'b1}}),
.address_a(waddr),
.address_b(raddr),
.clock0(wclk),
.clock1(rclk),
.clocken0(1'b1),
.clocken1(1'b1),
.aclr0(1'b0),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a({{1'b1}}),
.byteena_b({{1'b1}}),
.q_a(),
.q_b(rdata[(DATA_SIZE / (DDR_MODE + 1))-1:0])
);
// reset synchronizers
always @(negedge npor or posedge rclk)
begin
if (npor == 1'b0)
begin
npor_rd_r <= 0;
npor_rd_rr <= 0;
end
else
begin
npor_rd_r <= 1;
npor_rd_rr <= npor_rd_r;
end
end
always @(negedge npor or posedge wclk)
begin
if (npor == 1'b0)
begin
npor_wr_r <= 0;
npor_wr_rr <= 0;
end
else
begin
npor_wr_r <= 1;
npor_wr_rr <= npor_wr_r;
end
end
//------------------------------------------------------------
// Read and Write address pointer keeps incrementing
// When write pointer is at "8", bit 3 of the address bus is
// propogated to the read side like a strobe.
// On the rising edge of this strobe, it should line up with read
// address pointer = 0x5 if the two clocks are the exact frequency
//----------------------------------------------------------
always @(negedge npor_rd_rr or posedge rclk)
begin
if (npor_rd_rr == 1'b0)
begin
raddr <= 4'h0 ;
strobe_r <= 1'b0 ;
strobe_rr <= 1'b0 ;
rerror <= 1'b0 ;
end
else
begin
strobe_r <= DDR_MODE ? waddr[2] : waddr[3] ;
strobe_rr <= strobe_r ;
raddr <= raddr + 1'b1 ;
if (strobe_r == 1'b1 & strobe_rr == 1'b0 & (raddr > 4'h9))
begin
rerror <= 1'b1 ;
end
if (rerror == 1'b1)
begin
$display("PhaseFIFO Frequency mismatch Error!\n");
$stop;
end
end
end
always @(negedge npor_wr_rr or posedge wclk)
begin
if (npor_wr_rr == 1'b0)
begin
waddr <= DDR_MODE ? 3'h2 : 4'h4 ;
end
else
begin
waddr <= waddr + 1'b1;
end
end
endmodule
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Full Version
# Date created = 11:17:02 March 30, 2012
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "11:17:02 March 30, 2012"
# Revisions
PROJECT_REVISION = "pcie_wb"
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create_clock -period "125 MHz" -name {clk125_i} {clk125_i}
create_clock -period "100 MHz" -name {pcie_refclk_i} {pcie_refclk_i}
derive_pll_clocks
derive_clock_uncertainty
\ No newline at end of file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity pow_reset is
port (
clk: in std_logic; -- 125Mhz
nreset: buffer std_logic
);
end entity;
architecture pow_reset_arch of pow_reset is
signal powerOn: unsigned(6 downto 0) := "0000000"; -- 7Bit for 1ms nrst
begin
nres: process(Clk)
begin
if Clk'event and Clk = '1' then
if nreset = '0' then
powerOn <= powerOn + 1;
end if;
nReset <= std_logic(powerOn(powerON'high));
end if;
end process;
end architecture;
\ No newline at end of file
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