Skip to content

F
FPGA Configuration Space
Commit 496149d6 authored by bradomyn's avatar bradomyn
Browse files
Options

vme_wb: adding bit width emulation to the driver. 

The chip tundra doesn't support 8 bit data width transfer.
It's going to be emulated writing first in register of
the slave indicating the width
parent 6bc3341f
Hide whitespace changes
Inline Side-by-side
Showing with 26 additions and 14 deletions
vme-wb/vme_wb.c
View file @ 496149d6
......@@ -106,9 +106,12 @@ static void wb_write(struct wishbone *wb, wb_addr_t addr, wb_data_t data)
{
struct vme_wb_dev *dev;
unsigned char *reg_win;
unsigned char *ctrl_win;
dev = container_of(wb, struct vme_wb_dev, wb);
reg_win = dev->vme_res.map[MAP_REG]->kernel_va;
ctrl_win = dev->vme_res.map[MAP_CTRL]->kernel_va;
addr = addr << 2;
switch (dev->width) {
......@@ -116,19 +119,22 @@ static void wb_write(struct wishbone *wb, wb_addr_t addr, wb_data_t data)
if (unlikely(debug))
printk(KERN_ALERT VME_WB ": iowrite32(0x%x, 0x%x)\n",
data, addr);
iowrite32(swapbe32(EMUL_32_BIT), ctrl_win + EMUL_DAT_WD);
iowrite32(data, reg_win + addr);
break;
case 2:
if (unlikely(debug))
printk(KERN_ALERT VME_WB ": iowrite16(0x%x, 0x%x)\n",
data >> dev->shift, addr);
iowrite32(swapbe32(EMUL_16_BIT), ctrl_win + EMUL_DAT_WD);
iowrite16(data >> dev->shift, reg_win + addr);
break;
case 1:
if (unlikely(debug))
printk(KERN_ALERT VME_WB ": iowrite8(0x%x, 0x%x)\n",
data >> dev->shift, addr);
iowrite8(data >> dev->shift, reg_win + addr);
iowrite32(swapbe32(EMUL_8_BIT), ctrl_win + EMUL_DAT_WD);
iowrite32(data >> dev->shift, reg_win + addr);
break;
}
......
vme-wb/vme_wb.h
View file @ 496149d6
......@@ -18,30 +18,36 @@
#define VME_DEFAULT_IDX { [0 ... (VME_MAX_DEVICES-1)] = -1 }
/* VME CSR offsets */
#define FUN0ADER 0x7FF63
#define FUN1ADER 0x7FF73
#define WB_32_64 0x7ff33
#define FUN0ADER 0x7FF63
#define FUN1ADER 0x7FF73
#define WB_32_64 0x7ff33
#define BIT_SET_REG 0x7FFFB
#define BIT_CLR_REG 0x7FFF7
#define IRQ_VECTOR 0x7FF5F
#define IRQ_LEVEL 0x7FF5B
#define IRQ_VECTOR 0x7FF5F
#define IRQ_LEVEL 0x7FF5B
#define VME_VENDOR_ID_OFFSET 0x24
/* VME CSR VALUES */
#define WB32 1
#define WB64 0
#define RESET_CORE 0x80
#define RESET_CORE 0x80
#define ENABLE_CORE 0x10
#define VME_IRQ_LEVEL 0x6
#define VME_VENDOR_ID 0x80031
/* VME WB Interdace*/
#define ERROR_FLAG 0
#define SDWB_ADDRESS 8
#define CTRL 16
#define MASTER_CTRL 24
#define MASTER_ADD 32
#define MASTER_DATA 40
/* VME WB Interdace */
#define ERROR_FLAG 0
#define SDWB_ADDRESS 8
#define CTRL 16
#define MASTER_CTRL 24
#define MASTER_ADD 32
#define MASTER_DATA 40
#define EMUL_DAT_WD 48
/* Data width emulation */
#define EMUL_8_BIT 1
#define EMUL_16_BIT 2
#define EMUL_32_BIT 3
enum vme_map_win {
MAP_CR_CSR = 0, /* CR/CSR */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment