Commits · 2f3cd5e026da55e91dc743d7fe695ba7db9db6cd · Projects / FPGA Configuration Space

Apr 13, 2012
- Work-around some sort of timing anomaly on the HardIP config space. · 2f3cd5e0
  Wesley W. Terpstra authored 12 years ago
  
  2f3cd5e0
- Strobe needs to be cut-through if data is. · 56b99dd0
  Wesley W. Terpstra authored 12 years ago
  
  56b99dd0
- working wishbone output! · 8feb4fc7
  Wesley W. Terpstra authored 12 years ago
  
  8feb4fc7
Apr 12, 2012
- Strip pad words introduced by the Altera HardIP · 1398bcdf
  Wesley W. Terpstra authored 12 years ago
  
  1398bcdf
- Split the Altera specific stuff into a distinct component · 480a61b8
  Wesley W. Terpstra authored 12 years ago
```
Implement a wishbone streaming interface bridge from the Avalon RX stream
```
  480a61b8
Apr 05, 2012
- Move HDL to a subfolder · 02b2341e
  Wesley W. Terpstra authored 12 years ago
```
Add driver stub code
```
  02b2341e
Apr 04, 2012
- added simple sdc · 5ca542aa
  Stefan Rauch authored 12 years ago
  
  5ca542aa
- Added Flash programmer · cec825c0
  Stefan Rauch authored 12 years ago
  
  cec825c0
- Added pins for LEDs · 1064e2ff
  Stefan Rauch authored 12 years ago
```
Modified PLL for two outputs
Added power on reset
Re-instantiated the PCIe megafunction
```
  1064e2ff
Apr 03, 2012
- connected busy bit of reconfig block. otherwise pcie is stuck in calibration · d98c7f50
  Stefan Rauch authored 12 years ago
  
  d98c7f50
- It seems you need all of these files too to build PCIe. · 0acf0c16
  Wesley W. Terpstra authored 12 years ago
  
  0acf0c16
- Import PCIe-WB project into git · 7595c06b
  Wesley W. Terpstra authored 12 years ago
  
  7595c06b