24-10-2011: 10 V2 boards will be assembled

added by Erik van der Bij on 2011-10-25 21:24:29.619621

After the recommended changes from the design review were made, twenty PCBs will be built. First only ten of them will be assembled. Preliminary tests will decide if the other ten will be assembled later.

06-10-2011: V2 layout ready. Needs review.

added by Erik van der Bij on 2011-10-10 11:00:47.366201

The layout of the V2 is ready. The schematics and PCB design will be reviewed by a team of at least 4 people. The changes are the result of many tests done before and the design review held in August. The new design will also be easier to produce.

16-08-2011: Schematics for V2 reviewed

added by Erik van der Bij on 2011-08-16 15:17:39.207135

Four designers have reviewed the schematics design of the V2 of the VFC card. The suggested changes will be integrated and will improve the design and manufacturability. By the end of August a new layout will be made.

10-08-2011: V2 schematics ready for review

added by Erik van der Bij on 2011-08-11 09:49:02.440090

The schematics have been updated to cover most of the issues found during the sprint. We will hold a review in the coming week.

17-06-2011: Sprinting bears fruit: 14 issues found

added by Erik van der Bij on 2011-06-17 14:21:32.055346

Since the Scrum sprint to quickly debug the design with four engineers, already fourteen hardware problems have been found. Many are small bugs, but it also has been found that the SFP serial inputs are not usable as the Tx and Rx part are swapped.

We are using the Issues feature of the Open Hardware site to keep track of all issues and make sure that they will be handled in future versions of the design.

07-06-2011: Sprint to debug fast

added by Erik van der Bij on 2011-06-09 11:02:42.638081

As the project is going slower than we want, we decided to start a sprint to debug the hardware design. For two to three weeks four engineers will be intensively working on testing and debugging the design. We follow the scrum methodology, meeting shortly every morning to decide on what work needs to be done on that day. The aim is to test the current design as quickly as possible and to collect info for the next version of the design.

11-04-2011: small production finds assembly problems

added by Erik van der Bij on 2011-04-11 09:46:16.905532

To allow other people to start developments for the VFC card, ten additional boards have been produced. During the assembly, problems with the FMC connectors appeared that could be circumvented by using a thicker stencil (that will apply more solder) and then reworking some capacitors manually. For new productions the layout will need to be modified to allow more spacing between these capacitors. At the same time the JTAG chain that programs the two FPGAs will be split into two seperate chains as there have been some programming problems. The modification work on the layout will start in two or three weeks time.

Currently there are four boards working while an additional eight boards need rework.

17-02-2011: PLL test: they work

added by Andrea Boccardi on 2011-02-17 12:07:04.071697

The pll access have been tested. It is working and the PLLs have been configured to work at a few frequencies(66.6, 100, 200, 400MHz).

10-02-2011: Voltage monitoring ADC tested: OK

added by Andrea Boccardi on 2011-02-10 16:42:08.441146

Voltage monitoring ADC tested: ok

09-02-2011: VDADJ1 control tested

added by Andrea Boccardi on 2011-02-09 13:55:08.015099

The VADJ control has been tested. It is possible to set using the digital potentiometer between 1.2V and 3.3V

09-02-2011: SRAM tested with 100MHz accesses working fine

added by Andrea Boccardi on 2011-02-09 13:53:47.397985

The 2 external SRAMS have been tested with several patterns and accesses at 100MHz.

20-12-2010: FPGA programming OK. VME access works.

added by Erik van der Bij on 2010-12-20 09:46:32.543620

Test code is loaded in the System FPGA and the PROM is programmed. Both JTAG and PROM loading are working. VME access works using the same VME core as used on the DAB module. This VME core later will be replaced by a more modern VME64x core.

09-11-2010: 2nd prototype powered

added by Andrea Boccardi on 2010-11-09 17:05:42.382833

All the power supply are working on this one. It is issued from a different batch of PCBs.

09-11-2010: 1st board powered...

added by Andrea Boccardi on 2010-11-09 17:01:54.790424

The 1st prototype has been powered.
3 DC/DC (Vadj2, V1.5 and Vadj1) are not working. A cold soldering has been detected on one of the FB resistors. Re-soldering it didn't solve the problem. The 3 modules involved are misaligned respect to the soldering pads.
All the inputs are at the right value and no shorts have been detected.

19-10-2010: 1st assembled board received

added by Andrea Boccardi on 2010-10-20 10:59:21.527693

1st assembled board received, the front panel should come soon.

15-10-2010: One assembled board in a week's time

added by Erik van der Bij on 2010-10-15 11:41:09.528482

The prototyping process found already a small problem with the specification of the solder mask of the 0402 capacitors under the BGAs. This will be corrected. One prototype board with the old masks will be provided on 22 October.

05-07-2010: PCB layout review held

added by Erik van der Bij on 2010-07-05 17:46:50.072390

The PCB layout review has been held (3 people from BE/CO reviewed) and some minor issues have been raised that may improve signal quality and some estethics of the board.

01-07-2010: PCB layout review scheduled for 5 July.

added by Erik van der Bij on 2010-07-01 16:26:53.543603

Three persons from BE/CO have reviewed the PCB layout. The possible improvements will be discussed on 5 July.

23-06-2010: Layout files received and being reviewed

added by Andrea Boccardi on 2010-06-25 09:23:49.477612

The PCB layout is finished and is being reviewed. If no major issues will be found the production will be launched for the beginning of July. Layout time was about 320 hours.

22-06-2010: Layout almost finished

added by Erik van der Bij on 2010-06-22 14:17:17.420366

The PCB layout is almost finished. The stackup has been changed to have no two signal layers next to each other (reducing crosstalk).

18-05-2010: All 0.1% resistors replaced by 1%

added by Erik van der Bij on 2010-05-18 10:06:26.515309

When going through the bill of material, we found that over 15 0.1% resistors where used. A more careful analysis found out that standard 1% resistors could do the job. This will be modified before PCB layout is finished. It will result in a cost saving.

11-05-2010: All active components ordered

added by Erik van der Bij on 2010-05-11 15:05:06.158909

All active components have been ordered and the component list has been re-verified (one component was forgotten to be ordered).
Unfortunately the ZBT RAM used will become obsolete as orders will only be possible until November 2010. To advance the project the component used will not be changed, but a redesign of the project has to be foreseen for this memory.
Some non-critical components will be delivered only in July (DAC for setting VCO voltage) or even August (+5 to negative voltage converter).

10-05-2010: Vadj fixed to 2.5V for FMC slot 2

added by Erik van der Bij on 2010-05-10 10:30:06.822097

After careful checking it was made possible to fix Vadj of FMC slot 2 to 2.5V so that the ADC card under development can also be used on this slot.
Unfortunately two differential lines had to be dropped and the JTAG chain of FMC slots is now part of the internal JEDEC test chain, so one cannot test remotely.

28-04-2010: Vadj will be fixed to 3.3 Volt for FMC slot 2

added by Erik van der Bij on 2010-04-28 17:15:13.312948

Because of a problem with the I/O levels of the different banks in the Xilinx, Vadj will need to be fixed at 3.3 Volt for Slot 2. The schematic will need to be changed for this as otherwise Slot 2 could not drive LVDS signals. Update: has become 2.5V

The layout work started week 15.

added by Andrea Boccardi on 2010-04-12 09:13:13.464945

The layout work started week 15.
It was possible to place all the desired components on the front panel, it remains just to verify the tolerances.
From a preliminary placement the board seems dense but the only 2 components that seems to cause some troubles are the 2 inverting DC/DC.

24-03-2010 - PCB layout started

added by Erik van der Bij on 2010-03-25 15:17:15.036528

The schematics have been sent to the layout office. The PCB layout work will start in the first week of April and will be ready by the end of May, ready to be reviewed before production.