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VME FMC Carrier VFC
Commits
88e03536
Commit
88e03536
authored
Jan 10, 2011
by
Andrea Boccardi
Browse files
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Plain Diff
Added a simple SRAM controller in the Application FPGA
parent
cb70c6e4
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Showing
8 changed files
with
261 additions
and
53 deletions
+261
-53
AddrDecoderWBApp.v
trunk/hdl/design/AddrDecoderWBApp.v
+26
-10
ApplicationFpga.v
trunk/hdl/design/ApplicationFpga.v
+76
-6
WbToCy7c1470.v
trunk/hdl/design/WbToCy7c1470.v
+51
-0
VFCBoard.v
trunk/hdl/schematic/VFCBoard.v
+57
-2
makefile
trunk/simulation/makefile
+2
-0
VfcRegistersMap.py
trunk/software/VfcRegistersMap.py
+9
-2
VmeFunctions.py
trunk/software/VmeFunctions.py
+11
-1
mysim.py
trunk/software/mysim.py
+29
-32
No files found.
trunk/hdl/design/AddrDecoderWBApp.v
View file @
88e03536
module
AddressDecoderWBApp
(
module
AddressDecoderWBApp
(
input
Clk_ik
,
input
[
20
:
0
]
Adr_ib21
,
input
[
20
:
0
]
Adr_ib21
,
input
Stb_i
,
input
Stb_i
,
output
reg
[
31
:
0
]
Dat_ob32
,
output
reg
[
31
:
0
]
Dat_ob32
,
output
Ack_o
,
output
reg
Ack_o
,
input
[
31
:
0
]
DatDebugRegs_ib32
,
input
[
31
:
0
]
DatDebugRegs_ib32
,
input
AckDebugRegs_i
,
input
AckDebugRegs_i
,
output
reg
StbDebugRegs_o
)
;
output
reg
StbDebugRegs_o
,
assign
Ack_o
=
AckDebugRegs_i
;
input
[
31
:
0
]
DatSram1Controller_ib32
,
input
AckSram1Controller_i
,
output
reg
StbSram1Controller_o
,
always
@*
begin
input
[
31
:
0
]
DatSram2Controller_ib32
,
StbDebugRegs_o
=
1'b0
;
input
AckSram2Controller_i
,
Dat_ob32
=
32'h0
;
output
reg
StbSram2Controller_o
)
;
if
(
Adr_ib21
[
20
:
2
]
==
'h0
)
begin
// FROM 0_0000 TO 0_0003 (WB) == FROM 80_0000 TO 80_000C (VME) <- 4 regs (16B)
StbDebugRegs_o
=
Stb_i
;
always
@
(
posedge
Clk_ik
)
begin
Dat_ob32
=
DatDebugRegs_ib32
;
Ack_o
<=
AckDebugRegs_i
||
AckSram1Controller_i
||
AckSram2Controller_i
;
end
Dat_ob32
<=
32'h0
;
StbDebugRegs_o
<=
1'b0
;
StbSram1Controller_o
<=
1'b0
;
StbSram2Controller_o
<=
1'b0
;
if
(
Adr_ib21
[
20
:
2
]
==
'h0
)
begin
// FROM 00_0000 TO 00_0003 (WB) == FROM 80_0000 TO 80_000C (VME) <- 4 regs (16B)
StbDebugRegs_o
<=
Stb_i
;
Dat_ob32
<=
DatDebugRegs_ib32
;
end
else
if
(
Adr_ib21
[
20
:
19
]
==
2'h1
)
begin
// FROM 08_0000 TO 0F_FFFF == FROM A0_0000 TO BF_FFFC (VME)
StbSram1Controller_o
<=
Stb_i
;
Dat_ob32
<=
DatSram1Controller_ib32
;
end
else
if
(
Adr_ib21
[
20
:
19
]
==
2'h2
)
begin
// FROM 10_0000 TO 17_FFFF == FROM C0_0000 TO DF_FFFC (VME)
StbSram2Controller_o
<=
Stb_i
;
Dat_ob32
<=
DatSram2Controller_ib32
;
end
end
end
endmodule
endmodule
trunk/hdl/design/ApplicationFpga.v
View file @
88e03536
...
@@ -13,19 +13,37 @@ module ApplicationFpga(
...
@@ -13,19 +13,37 @@ module ApplicationFpga(
inout
AFpgaProgRdWr_io
,
inout
AFpgaProgRdWr_io
,
inout
AFpgaProgInit_io
,
inout
AFpgaProgInit_io
,
inout
[
35
:
0
]
Sram1Data_b36
,
output
[
20
:
0
]
Sram1Address_b21
,
output
Sram1Clk_k
,
output
Sram1We_n
,
output
Sram1Oe_n
,
output
[
3
:
0
]
Sram1Bws_nb4
,
inout
[
35
:
0
]
Sram2Data_b36
,
output
[
20
:
0
]
Sram2Address_b21
,
output
Sram2Clk_k
,
output
Sram2We_n
,
output
Sram2Oe_n
,
output
[
3
:
0
]
Sram2Bws_nb4
,
inout
[
4
:
1
]
FpGpIo_iob4
,
inout
[
4
:
1
]
FpGpIo_iob4
,
input
PushButton_ion
)
;
input
PushButton_ion
)
;
`define
dly
#
1
`define
dly
#
1
reg
Rst_rq
;
reg
Rst_rq
;
wire
[
20
:
0
]
Adr_b21
;
wire
[
20
:
0
]
Adr_b21
;
wire
Cyc
,
We
,
StbMaster
,
AckMaster
;
wire
Cyc
,
We
,
StbMaster
,
AckMaster
;
wire
[
31
:
0
]
DatMasterO_b32
,
DatMasterI_b32
;
wire
[
31
:
0
]
DatMasterO_b32
,
DatMasterI_b32
;
wire
[
31
:
0
]
DebugReg0
,
DebugReg1
,
DebugReg2
,
DebugReg3
;
wire
[
31
:
0
]
DebugReg0
,
DebugReg1
,
DebugReg2
,
DebugReg3
;
wire
[
31
:
0
]
DatDebugRegsrO_b32
;
wire
[
31
:
0
]
DatDebugRegsrO_b32
;
wire
StbDebugRegs
,
AckDebugRegs
;
wire
StbDebugRegs
,
AckDebugRegs
;
wire
StbSram1Controller
,
AckSram1Controller
;
wire
[
31
:
0
]
DatSram1ControllerO_b32
;
wire
StbSram2Controller
,
AckSram2Controller
;
wire
[
31
:
0
]
DatSram2ControllerO_b32
;
//#####################################
//#####################################
// Clock
// Clock
...
@@ -52,7 +70,7 @@ always @(posedge Clk_k) Rst_rq <= `dly ~DeboucedPushButton_q || RstWB;
...
@@ -52,7 +70,7 @@ always @(posedge Clk_k) Rst_rq <= `dly ~DeboucedPushButton_q || RstWB;
assign
FpGpIo_iob4
[
4
]
=
Clk_k
;
assign
FpGpIo_iob4
[
4
]
=
Clk_k
;
assign
FpGpIo_iob4
[
3
]
=
Rst_rq
;
assign
FpGpIo_iob4
[
3
]
=
Rst_rq
;
assign
FpGpIo_iob4
[
2
]
=
We
&&
Cyc
&&
StbDebugRegs
;
assign
FpGpIo_iob4
[
2
]
=
We
&&
Cyc
&&
StbDebugRegs
;
assign
FpGpIo_iob4
[
1
]
=
1'bz
;
assign
FpGpIo_iob4
[
1
]
=
1'bz
;
//#####################################
//#####################################
// WishBone Serial Interface
// WishBone Serial Interface
...
@@ -78,6 +96,7 @@ Ser2MstWB i_Ser2MstWB(
...
@@ -78,6 +96,7 @@ Ser2MstWB i_Ser2MstWB(
AddressDecoderWBApp
i_AddressDecoderWB
(
AddressDecoderWBApp
i_AddressDecoderWB
(
.
Clk_ik
(
Clk_k
)
,
.
Adr_ib21
(
Adr_b21
)
,
.
Adr_ib21
(
Adr_b21
)
,
.
Stb_i
(
StbMaster
)
,
.
Stb_i
(
StbMaster
)
,
.
Dat_ob32
(
DatMasterI_b32
)
,
.
Dat_ob32
(
DatMasterI_b32
)
,
...
@@ -85,13 +104,21 @@ AddressDecoderWBApp i_AddressDecoderWB(
...
@@ -85,13 +104,21 @@ AddressDecoderWBApp i_AddressDecoderWB(
.
DatDebugRegs_ib32
(
DatDebugRegsrO_b32
)
,
.
DatDebugRegs_ib32
(
DatDebugRegsrO_b32
)
,
.
AckDebugRegs_i
(
AckDebugRegs
)
,
.
AckDebugRegs_i
(
AckDebugRegs
)
,
.
StbDebugRegs_o
(
StbDebugRegs
))
;
.
StbDebugRegs_o
(
StbDebugRegs
)
,
.
DatSram1Controller_ib32
(
DatSram1ControllerO_b32
)
,
.
AckSram1Controller_i
(
AckSram1Controller
)
,
.
StbSram1Controller_o
(
StbSram1Controller
)
,
.
DatSram2Controller_ib32
(
DatSram2ControllerO_b32
)
,
.
AckSram2Controller_i
(
AckSram2Controller
)
,
.
StbSram2Controller_o
(
StbSram2Controller
))
;
//#####################################
//#####################################
// Debug Registers
// Debug Registers
//#####################################
//#####################################
Generic4OutputRegs
#(
.
Reg0Default
(
32'ha
)
,
.
Reg1Default
(
32'hb
)
,
.
Reg2Default
(
32'hc
)
,
.
Reg3Default
(
32'hd
))
Generic4OutputRegs
#(
.
Reg0Default
(
32'ha
)
,
.
Reg1Default
(
32'hb
)
,
.
Reg2Default
(
32'hc
)
,
.
Reg3Default
(
32'hd
))
i_DebugRegs
(
i_DebugRegs
(
.
Rst_irq
(
Rst_rq
)
,
.
Rst_irq
(
Rst_rq
)
,
.
Clk_ik
(
Clk_k
)
,
.
Clk_ik
(
Clk_k
)
,
...
@@ -107,4 +134,47 @@ i_DebugRegs(
...
@@ -107,4 +134,47 @@ i_DebugRegs(
.
Reg2Value_ob32
(
DebugReg2
)
,
.
Reg2Value_ob32
(
DebugReg2
)
,
.
Reg3Value_ob32
(
DebugReg3
))
;
.
Reg3Value_ob32
(
DebugReg3
))
;
//#####################################
// Sram Controllers
//#####################################
wire
[
20
:
0
]
AdrSram1Controller
=
{
2'b0
,
Adr_b21
[
18
:
0
]
};
WbToCy7c1470
i_Sram1Controller
(
.
Rst_irq
(
Rst_rq
)
,
.
Clk_ik
(
Clk_k
)
,
.
Cyc_i
(
Cyc
)
,
.
Stb_i
(
StbSram1Controller
)
,
.
We_i
(
We
)
,
.
Adr_ib21
(
AdrSram1Controller
)
,
.
Dat_ib32
(
DatMasterO_b32
)
,
.
Dat_ob32
(
DatSram1ControllerO_b32
)
,
.
Ack_oa
(
AckSram1Controller
)
,
.
SramData_iob36
(
Sram1Data_b36
)
,
.
SramAddress_ob21
(
Sram1Address_b21
)
,
.
SramClk_ok
(
Sram1Clk_k
)
,
.
SramWe_on
(
Sram1We_n
)
,
.
SramOe_on
(
Sram1Oe_n
)
,
.
SramBws_onb4
(
Sram1Bws_nb4
))
;
wire
[
20
:
0
]
AdrSram2Controller
=
{
2'b0
,
Adr_b21
[
18
:
0
]
};
WbToCy7c1470
i_Sram2Controller
(
.
Rst_irq
(
Rst_rq
)
,
.
Clk_ik
(
Clk_k
)
,
.
Cyc_i
(
Cyc
)
,
.
Stb_i
(
StbSram2Controller
)
,
.
We_i
(
We
)
,
.
Adr_ib21
(
AdrSram2Controller
)
,
.
Dat_ib32
(
DatMasterO_b32
)
,
.
Dat_ob32
(
DatSram2ControllerO_b32
)
,
.
Ack_oa
(
AckSram2Controller
)
,
.
SramData_iob36
(
Sram2Data_b36
)
,
.
SramAddress_ob21
(
Sram2Address_b21
)
,
.
SramClk_ok
(
Sram2Clk_k
)
,
.
SramWe_on
(
Sram2We_n
)
,
.
SramOe_on
(
Sram2Oe_n
)
,
.
SramBws_onb4
(
Sram2Bws_nb4
))
;
endmodule
endmodule
trunk/hdl/design/WbToCy7c1470.v
0 → 100644
View file @
88e03536
module
WbToCy7c1470
(
input
Rst_irq
,
input
Clk_ik
,
input
Cyc_i
,
input
Stb_i
,
input
We_i
,
input
[
20
:
0
]
Adr_ib21
,
input
[
31
:
0
]
Dat_ib32
,
output
reg
[
31
:
0
]
Dat_ob32
,
output
Ack_oa
,
inout
[
35
:
0
]
SramData_iob36
,
output
reg
[
20
:
0
]
SramAddress_ob21
,
output
SramClk_ok
,
output
SramWe_on
,
output
SramOe_on
,
output
[
3
:
0
]
SramBws_onb4
)
;
reg
[
3
:
0
]
ReadCycle_d
;
reg
[
31
:
0
]
DatI_db32
[
2
:
0
]
;
reg
[
2
:
0
]
WriteCycle_d
;
wire
ReadCycle_a
=
Cyc_i
&&
Stb_i
&&
~
We_i
;
wire
WriteCycle_a
=
Cyc_i
&&
Stb_i
&&
We_i
;
always
@
(
posedge
Clk_ik
)
ReadCycle_d
<=
{
ReadCycle_d
[
2
:
0
]
,
ReadCycle_a
};
assign
Ack_oa
=
WriteCycle_a
||
(
ReadCycle_a
&&
ReadCycle_d
[
3
])
;
assign
SramOe_on
=
~
ReadCycle_d
[
2
]
;
always
@
(
posedge
Clk_ik
)
SramAddress_ob21
<=
Adr_ib21
;
always
@
(
posedge
Clk_ik
)
WriteCycle_d
<=
{
WriteCycle_d
[
1
:
0
]
,
WriteCycle_a
};
assign
SramWe_on
=
~
WriteCycle_d
[
0
]
;
always
@
(
posedge
Clk_ik
)
begin
DatI_db32
[
2
]
<=
DatI_db32
[
1
]
;
DatI_db32
[
1
]
<=
DatI_db32
[
0
]
;
DatI_db32
[
0
]
<=
Dat_ib32
;
end
assign
SramData_iob36
=
WriteCycle_d
[
2
]
?
{
4'h0
,
DatI_db32
[
2
]
}
:
36
'
hz
;
always
@
(
posedge
Clk_ik
)
if
(
ReadCycle_d
[
2
])
Dat_ob32
<=
SramData_iob36
;
assign
SramClk_ok
=
Clk_ik
;
assign
SramBws_onb4
=
4'h0
;
endmodule
trunk/hdl/schematic/VFCBoard.v
View file @
88e03536
...
@@ -501,7 +501,17 @@ SystemFpga i_SystemFpga(
...
@@ -501,7 +501,17 @@ SystemFpga i_SystemFpga(
//##############################################################
//##############################################################
// APPLICATION FPGA
// APPLICATION FPGA
//##############################################################
//##############################################################
wire
[
35
:
0
]
Sram1Data_b36
;
wire
[
20
:
0
]
Sram1Address_b21
;
wire
Sram1Clk_k
,
Sram1We_n
,
Sram1Oe_n
;
wire
[
3
:
0
]
Sram1Bws_nb4
;
wire
[
35
:
0
]
Sram2Data_b36
;
wire
[
20
:
0
]
Sram2Address_b21
;
wire
Sram2Clk_k
,
Sram2We_n
,
Sram2Oe_n
;
wire
[
3
:
0
]
Sram2Bws_nb4
;
ApplicationFpga
i_ApplicationFpga
(
ApplicationFpga
i_ApplicationFpga
(
.
SysAppClk_ik
(
Sys2AppClk
)
,
.
SysAppClk_ik
(
Sys2AppClk
)
,
...
@@ -513,8 +523,21 @@ ApplicationFpga i_ApplicationFpga(
...
@@ -513,8 +523,21 @@ ApplicationFpga i_ApplicationFpga(
.
AFpgaProgM_iob2
(
AFpgaProgM_b2
)
,
.
AFpgaProgM_iob2
(
AFpgaProgM_b2
)
,
.
AFpgaProgCsi_io
(
AFpgaProgCsi
)
,
.
AFpgaProgCsi_io
(
AFpgaProgCsi
)
,
.
AFpgaProgRdWr_io
(
AFpgaProgRdWr
)
,
.
AFpgaProgRdWr_io
(
AFpgaProgRdWr
)
,
.
AFpgaProgInit_io
(
AFpgaProgInit
)
,
.
AFpgaProgInit_io
(
AFpgaProgInit
)
,
.
Sram1Data_b36
(
Sram1Data_b36
)
,
.
Sram1Address_b21
(
Sram1Address_b21
)
,
.
Sram1Clk_k
(
Sram1Clk_k
)
,
.
Sram1We_n
(
Sram1We_n
)
,
.
Sram1Oe_n
(
Sram1Oe_n
)
,
.
Sram1Bws_nb4
(
Sram1Bws_nb4
)
,
.
Sram2Data_b36
(
Sram2Data_b36
)
,
.
Sram2Address_b21
(
Sram2Address_b21
)
,
.
Sram2Clk_k
(
Sram2Clk_k
)
,
.
Sram2We_n
(
Sram2We_n
)
,
.
Sram2Oe_n
(
Sram2Oe_n
)
,
.
Sram2Bws_nb4
(
Sram2Bws_nb4
)
,
.
PushButton_ion
(
a_PushButton_n
)
,
.
PushButton_ion
(
a_PushButton_n
)
,
...
@@ -533,4 +556,36 @@ MAX5483 ic44(
...
@@ -533,4 +556,36 @@ MAX5483 ic44(
.
SclkInc_iqk
(
VAdjSClk_k
)
,
.
SclkInc_iqk
(
VAdjSClk_k
)
,
.
DinUD_iq
(
VAdjDin
))
;
.
DinUD_iq
(
VAdjDin
))
;
//##############################################################
// Memories (SRAM)
//##############################################################
cy7c1470
i_Sram1
(
.
d
(
Sram1Data_b36
)
,
.
clk
(
Sram1Clk_k
)
,
.
a
(
Sram1Address_b21
)
,
.
bws
(
Sram1Bws_nb4
)
,
.
we_b
(
Sram1We_n
)
,
.
adv_lb
(
Gnd
)
,
.
ce1b
(
Gnd
)
,
.
ce2
(
Vcc
)
,
.
ce3b
(
Gnd
)
,
.
oeb
(
Sram1Oe_n
)
,
.
cenb
(
Gnd
)
,
.
mode
(
Gnd
))
;
cy7c1470
i_Sram2
(
.
d
(
Sram2Data_b36
)
,
.
clk
(
Sram2Clk_k
)
,
.
a
(
Sram2Address_b21
)
,
.
bws
(
Sram2Bws_nb4
)
,
.
we_b
(
Sram2We_n
)
,
.
adv_lb
(
Gnd
)
,
.
ce1b
(
Gnd
)
,
.
ce2
(
Vcc
)
,
.
ce3b
(
Gnd
)
,
.
oeb
(
Sram2Oe_n
)
,
.
cenb
(
Gnd
)
,
.
mode
(
Gnd
))
;
endmodule
endmodule
trunk/simulation/makefile
View file @
88e03536
...
@@ -5,6 +5,7 @@ VerilogFiles=
...
@@ -5,6 +5,7 @@ VerilogFiles=
VerilogFiles
+=
../hdl/components/ivt3205c25mhz.v
VerilogFiles
+=
../hdl/components/ivt3205c25mhz.v
VerilogFiles
+=
../hdl/components/sn74vmeh22501.v
VerilogFiles
+=
../hdl/components/sn74vmeh22501.v
VerilogFiles
+=
../hdl/components/MAX5483.v
VerilogFiles
+=
../hdl/components/MAX5483.v
VerilogFiles
+=
../hdl/components/CY7C1470V33.v
# Components with missing models
# Components with missing models
VerilogFiles
+=
../hdl/components/blackboxes/si57x.v
VerilogFiles
+=
../hdl/components/blackboxes/si57x.v
# System FPGA's modules
# System FPGA's modules
...
@@ -22,6 +23,7 @@ VerilogFiles+= ../hdl/design/SpiMasterWB.v
...
@@ -22,6 +23,7 @@ VerilogFiles+= ../hdl/design/SpiMasterWB.v
VerilogFiles
+=
../hdl/design/ApplicationFpga.v
VerilogFiles
+=
../hdl/design/ApplicationFpga.v
VerilogFiles
+=
../hdl/design/Ser2MstWB.v
VerilogFiles
+=
../hdl/design/Ser2MstWB.v
VerilogFiles
+=
../hdl/design/AddrDecoderWBApp.v
VerilogFiles
+=
../hdl/design/AddrDecoderWBApp.v
VerilogFiles
+=
../hdl/design/WbToCy7c1470.v
# Board schematic
# Board schematic
VerilogFiles
+=
../hdl/schematic/VFCBoard.v
VerilogFiles
+=
../hdl/schematic/VFCBoard.v
# Simulation modules
# Simulation modules
...
...
trunk/software/VfcRegistersMap.py
View file @
88e03536
...
@@ -45,6 +45,13 @@ class VfcRegisters:
...
@@ -45,6 +45,13 @@ class VfcRegisters:
self
.
ApplDebugReg0
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x0
)
self
.
ApplDebugReg0
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x0
)
self
.
ApplDebugReg1
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x4
)
self
.
ApplDebugReg1
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x4
)
self
.
ApplDebugReg2
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x8
)
self
.
ApplDebugReg2
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x8
)
self
.
ApplDebugReg3
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0xC
)
self
.
ApplDebugReg3
=
VmeRegister
(
BoardBaseAddress
+
AFPGABaseAddress
+
0xC
)
#-----------------------
#Sram 1 (BA=0x80000)
#-----------------------
self
.
ApplSram1
=
VmeMemory
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x200000
)
#-----------------------
#Sram 2 (BA=0x100000)
#-----------------------
self
.
ApplSram2
=
VmeMemory
(
BoardBaseAddress
+
AFPGABaseAddress
+
0x400000
)
trunk/software/VmeFunctions.py
View file @
88e03536
...
@@ -6,7 +6,17 @@ class VmeRegister:
...
@@ -6,7 +6,17 @@ class VmeRegister:
def
Read
(
self
):
def
Read
(
self
):
Value
=
VmeRead
(
self
.
VmeAddr
)
Value
=
VmeRead
(
self
.
VmeAddr
)
return
Value
return
Value
class
VmeMemory
:
def
__init__
(
self
,
BaseAddr
):
self
.
VmeBaseAddr
=
BaseAddr
def
Write
(
self
,
Offset
,
Data
):
VmeWrite
(
self
.
VmeBaseAddr
+
Offset
,
Data
)
def
Read
(
self
,
Offset
):
Value
=
VmeRead
(
self
.
VmeBaseAddr
+
Offset
)
return
Value
def
VmeWrite
(
Addr
,
Data
):
def
VmeWrite
(
Addr
,
Data
):
MyString
=
'W '
+
hex
(
Addr
)[
2
:]
.
strip
(
'L'
)
+
' '
+
hex
(
Data
)[
2
:]
.
strip
(
'L'
)
+
'
\n
'
MyString
=
'W '
+
hex
(
Addr
)[
2
:]
.
strip
(
'L'
)
+
' '
+
hex
(
Data
)[
2
:]
.
strip
(
'L'
)
+
'
\n
'
fd_Out
=
open
(
'../simulation/Py2V.fifo'
,
'w'
)
fd_Out
=
open
(
'../simulation/Py2V.fifo'
,
'w'
)
...
...
trunk/software/mysim.py
View file @
88e03536
...
@@ -42,14 +42,10 @@ MyBoard.ApplDebugReg1.Write(0xb)
...
@@ -42,14 +42,10 @@ MyBoard.ApplDebugReg1.Write(0xb)
MyBoard
.
ApplDebugReg2
.
Write
(
0xc
)
MyBoard
.
ApplDebugReg2
.
Write
(
0xc
)
MyBoard
.
ApplDebugReg3
.
Write
(
0xd
)
MyBoard
.
ApplDebugReg3
.
Write
(
0xd
)
Value
=
hex
(
MyBoard
.
ApplDebugReg0
.
Read
())
print
"Application FPGA debug register 0 is: "
,
hex
(
MyBoard
.
ApplDebugReg0
.
Read
())
print
"Application FPGA debug register 0 is: "
,
Value
print
"Application FPGA debug register 1 is: "
,
hex
(
MyBoard
.
ApplDebugReg1
.
Read
())
Value
=
hex
(
MyBoard
.
ApplDebugReg1
.
Read
())
print
"Application FPGA debug register 2 is: "
,
hex
(
MyBoard
.
ApplDebugReg2
.
Read
())
print
"Application FPGA debug register 1 is: "
,
Value
print
"Application FPGA debug register 3 is: "
,
hex
(
MyBoard
.
ApplDebugReg3
.
Read
())
Value
=
hex
(
MyBoard
.
ApplDebugReg2
.
Read
())
print
"Application FPGA debug register 2 is: "
,
Value
Value
=
hex
(
MyBoard
.
ApplDebugReg3
.
Read
())
print
"Application FPGA debug register 3 is: "
,
Value
WaitSimulation
(
10000
)
WaitSimulation
(
10000
)
...
@@ -65,23 +61,19 @@ print "Checking the SPI master with short accesses with all the CPol CPha combin
...
@@ -65,23 +61,19 @@ print "Checking the SPI master with short accesses with all the CPol CPha combin
print
""
print
""
print
"SPI access CPol=0 CPha=0 MSB1st 8bit 0xaa halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=0 MSB1st 8bit 0xaa halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
0
,
8
,
0xaa
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
0
,
8
,
0xaa
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=0 CPha=1 MSB1st 8bit 0xcc halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=1 MSB1st 8bit 0xcc halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
1
,
0
,
8
,
0xcc
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
1
,
0
,
8
,
0xcc
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=1 CPha=0 MSB1st 8bit 0x55 halfperiod=4 wait=12"
print
"SPI access CPol=1 CPha=0 MSB1st 8bit 0x55 halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
1
,
0
,
0
,
8
,
0x55
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
1
,
0
,
0
,
8
,
0x55
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=1 CPha=1 MSB1st 8bit 0x66 halfperiod=4 wait=12"
print
"SPI access CPol=1 CPha=1 MSB1st 8bit 0x66 halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
1
,
1
,
0
,
8
,
0x66
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
1
,
1
,
0
,
8
,
0x66
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
WaitSimulation
(
10000
)
WaitSimulation
(
10000
)
...
@@ -91,23 +83,19 @@ print "Checking the SPI master with short accesses with all the CPol CPha combin
...
@@ -91,23 +83,19 @@ print "Checking the SPI master with short accesses with all the CPol CPha combin
print
""
print
""
print
"SPI access CPol=0 CPha=0 LSB1st 8bit 0xaa halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=0 LSB1st 8bit 0xaa halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
1
,
8
,
0xaa
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
1
,
8
,
0xaa
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=0 CPha=1 LSB1st 8bit 0xcc halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=1 LSB1st 8bit 0xcc halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
1
,
1
,
8
,
0xcc
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
1
,
1
,
8
,
0xcc
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=1 CPha=0 LSB1st 8bit 0x55 halfperiod=4 wait=12"
print
"SPI access CPol=1 CPha=0 LSB1st 8bit 0x55 halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
1
,
0
,
1
,
8
,
0x55
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
1
,
0
,
1
,
8
,
0x55
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=1 CPha=1 LSB1st 8bit 0x66 halfperiod=4 wait=12"
print
"SPI access CPol=1 CPha=1 LSB1st 8bit 0x66 halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
1
,
1
,
1
,
8
,
0x66
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
1
,
1
,
1
,
8
,
0x66
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
WaitSimulation
(
10000
)
WaitSimulation
(
10000
)
...
@@ -117,13 +105,11 @@ print "Checking with long access both CPha (only one CPol) MSB1st"
...
@@ -117,13 +105,11 @@ print "Checking with long access both CPha (only one CPol) MSB1st"
print
""
print
""
print
"SPI access CPol=0 CPha=0 MSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=0 MSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
0
,
68
,
0x1111222233334444a
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
0
,
68
,
0x1111222233334444a
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=0 CPha=1 MSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=1 MSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
0
,
68
,
0x1111222233334444a
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
0
,
68
,
0x1111222233334444a
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
WaitSimulation
(
10000
)
WaitSimulation
(
10000
)
...
@@ -133,13 +119,11 @@ print "Checking with long access both CPha (only one CPol) LSB1st"
...
@@ -133,13 +119,11 @@ print "Checking with long access both CPha (only one CPol) LSB1st"
print
""
print
""
print
"SPI access CPol=0 CPha=0 LSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=0 LSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
1
,
68
,
0x1111222233334444a
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
1
,
68
,
0x1111222233334444a
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
print
""
print
""
print
"SPI access CPol=0 CPha=1 LSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
print
"SPI access CPol=0 CPha=1 LSB1st 68bit 0x1111222233334444a halfperiod=4 wait=12"
Value
=
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
1
,
68
,
0x1111222233334444a
,
4
,
12
)
print
"Read "
,
hex
(
MyBoard
.
SpiAccess
(
31
,
0
,
0
,
1
,
68
,
0x1111222233334444a
,
4
,
12
))
print
"Read "
,
hex
(
Value
)
WaitSimulation
(
10000
)
WaitSimulation
(
10000
)
...
@@ -161,6 +145,19 @@ MyBoard.SaveVadjWiper()
...
@@ -161,6 +145,19 @@ MyBoard.SaveVadjWiper()
WaitSimulation
(
10000
)
WaitSimulation
(
10000
)
print
"Setting the Application FPGA SRAM1(0), SRAM1(1), SRAM2(0), SRAM2(1) to 3 to: 0x1a, 0x1b, 0x2a, 0x2b"
MyBoard
.
ApplSram1
.
Write
(
0
,
0x1a
)
MyBoard
.
ApplSram1
.
Write
(
4
,
0x1b
)
MyBoard
.
ApplSram2
.
Write
(
0
,
0x2a
)
MyBoard
.
ApplSram2
.
Write
(
4
,
0x2b
)
print
"Application FPGA SRAM1(0)is: "
,
hex
(
MyBoard
.
ApplSram1
.
Read
(
0
))
print
"Application FPGA SRAM1(1)is: "
,
hex
(
MyBoard
.
ApplSram1
.
Read
(
4
))
print
"Application FPGA SRAM2(0)is: "
,
hex
(
MyBoard
.
ApplSram2
.
Read
(
0
))
print
"Application FPGA SRAM2(1)is: "
,
hex
(
MyBoard
.
ApplSram2
.
Read
(
4
))
WaitSimulation
(
10000
)
StopSimulation
()
StopSimulation
()
exit
()
exit
()
Write
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