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VME FMC Carrier VFC
Commits
77de1364
Commit
77de1364
authored
Jan 06, 2011
by
Andrea Boccardi
Browse files
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Plain Diff
change of VmeInt in simulation
parent
33c447a0
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Showing
8 changed files
with
90 additions
and
10 deletions
+90
-10
ApplicationFpga.gise
...k/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.gise
+2
-0
ApplicationFpga_summary.html
...re/XilinxISE/ApplicationFpga/ApplicationFpga_summary.html
+8
-0
pn_parser.xmsgs
...firmware/XilinxISE/ApplicationFpga/_xmsgs/pn_parser.xmsgs
+18
-0
ApplicationFpga.projectmgr
...xISE/ApplicationFpga/iseconfig/ApplicationFpga.projectmgr
+18
-2
ApplicationFpga.xreport
...linxISE/ApplicationFpga/iseconfig/ApplicationFpga.xreport
+4
-0
SystemFpga.v
trunk/hdl/design/SystemFpga.v
+38
-6
makefile
trunk/simulation/makefile
+1
-1
mysim.py
trunk/software/mysim.py
+1
-1
No files found.
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga.gise
View file @
77de1364
...
@@ -133,6 +133,8 @@
...
@@ -133,6 +133,8 @@
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<status
xil_pn:value=
"OutOfDateForOutputs"
/>
<status
xil_pn:value=
"OutputChanged"
/>
<outfile
xil_pn:name=
"ApplicationFpga.bld"
/>
<outfile
xil_pn:name=
"ApplicationFpga.bld"
/>
<outfile
xil_pn:name=
"ApplicationFpga.ngd"
/>
<outfile
xil_pn:name=
"ApplicationFpga.ngd"
/>
<outfile
xil_pn:name=
"ApplicationFpga_ngdbuild.xrpt"
/>
<outfile
xil_pn:name=
"ApplicationFpga_ngdbuild.xrpt"
/>
...
...
trunk/firmware/XilinxISE/ApplicationFpga/ApplicationFpga_summary.html
View file @
77de1364
...
@@ -2,7 +2,11 @@
...
@@ -2,7 +2,11 @@
<BODY
TEXT=
'#000000'
BGCOLOR=
'#FFFFFF'
LINK=
'#0000EE'
VLINK=
'#551A8B'
ALINK=
'#FF0000'
>
<BODY
TEXT=
'#000000'
BGCOLOR=
'#FFFFFF'
LINK=
'#0000EE'
VLINK=
'#551A8B'
ALINK=
'#FF0000'
>
<TABLE
BORDER
CELLSPACING=
0
CELLPADDING=
3
WIDTH=
'100%'
>
<TABLE
BORDER
CELLSPACING=
0
CELLPADDING=
3
WIDTH=
'100%'
>
<TR
ALIGN=
CENTER
BGCOLOR=
'#99CCFF'
>
<TR
ALIGN=
CENTER
BGCOLOR=
'#99CCFF'
>
<
<<<<<<
.
mine
<
TD
ALIGN=
CENTER
COLSPAN=
'4'
><B>
ApplicationFpga Project Status
</B></TD></TR>
=======
<TD
ALIGN=
CENTER
COLSPAN=
'4'
><B>
ApplicationFpga Project Status (12/20/2010 - 15:25:46)
</B></TD></TR>
<TD
ALIGN=
CENTER
COLSPAN=
'4'
><B>
ApplicationFpga Project Status (12/20/2010 - 15:25:46)
</B></TD></TR>
>>>>>>> .r43
<TR
ALIGN=
LEFT
>
<TR
ALIGN=
LEFT
>
<TD
BGCOLOR=
'#FFFF99'
><B>
Project File:
</B></TD>
<TD
BGCOLOR=
'#FFFF99'
><B>
Project File:
</B></TD>
<TD>
ApplicationFpga.xise
</TD>
<TD>
ApplicationFpga.xise
</TD>
...
@@ -449,5 +453,9 @@ System Settings</A>
...
@@ -449,5 +453,9 @@ System Settings</A>
</TABLE>
</TABLE>
<
<<<<<<
.
mine
<
br
><center><b>
Date Generated:
</b>
12/20/2010 - 12:22:47
</center>
=======
<br><center><b>
Date Generated:
</b>
12/20/2010 - 15:25:46
</center>
<br><center><b>
Date Generated:
</b>
12/20/2010 - 15:25:46
</center>
>>>>>>> .r43
</BODY></HTML>
</BODY></HTML>
\ No newline at end of file
trunk/firmware/XilinxISE/ApplicationFpga/_xmsgs/pn_parser.xmsgs
View file @
77de1364
...
@@ -8,8 +8,26 @@
...
@@ -8,8 +8,26 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<messages>
<<<<<<
< .mine
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1648"
><arg
fmt=
"%s"
index=
"1"
>
Analyzing Verilog file \
"
C:/VFC_SVN/hdl/design/AddrDecoderWBApp.v\
"
into library work
</arg>
</msg>
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1648"
><arg
fmt=
"%s"
index=
"1"
>
Analyzing Verilog file \
"
C:/VFC_SVN/hdl/design/ApplicationFpga.v\
"
into library work
</arg>
</msg>
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1648"
><arg
fmt=
"%s"
index=
"1"
>
Analyzing Verilog file \
"
C:/VFC_SVN/hdl/design/Debouncer.v\
"
into library work
</arg>
</msg>
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1648"
><arg
fmt=
"%s"
index=
"1"
>
Analyzing Verilog file \
"
C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\
"
into library work
</arg>
</msg>
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1648"
><arg
fmt=
"%s"
index=
"1"
>
Analyzing Verilog file \
"
C:/VFC_SVN/hdl/design/Ser2MstWB.v\
"
into library work
</arg>
</msg>
=======
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1648"
><arg
fmt=
"%s"
index=
"1"
>
Analyzing Verilog file \
"
C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\
"
into library work
</arg>
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1648"
><arg
fmt=
"%s"
index=
"1"
>
Analyzing Verilog file \
"
C:/VFC_SVN/hdl/design/Generic4OutputRegs.v\
"
into library work
</arg>
</msg>
</msg>
>>>>>>> .r43
</messages>
</messages>
trunk/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.projectmgr
View file @
77de1364
...
@@ -38,7 +38,7 @@
...
@@ -38,7 +38,7 @@
<SelectedItems/>
<SelectedItems/>
<ScrollbarPosition
orientation=
"vertical"
>
0
</ScrollbarPosition>
<ScrollbarPosition
orientation=
"vertical"
>
0
</ScrollbarPosition>
<ScrollbarPosition
orientation=
"horizontal"
>
0
</ScrollbarPosition>
<ScrollbarPosition
orientation=
"horizontal"
>
0
</ScrollbarPosition>
<ViewHeaderState
orientation=
"horizontal"
>
000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000
420000000100000000000000240000000100000000000000660000000100000000000002d7
0000000100000000
</ViewHeaderState>
<ViewHeaderState
orientation=
"horizontal"
>
000000ff000000000000000100000000000000000100000000000000000000000000000000000003a3000000040101000100000000000000000000000064ffffffff000000810000000000000004000000
7c000000010000000000000089000000010000000000000066000000010000000000000238
0000000100000000
</ViewHeaderState>
<UserChangedColumnWidths
orientation=
"horizontal"
>
false
</UserChangedColumnWidths>
<UserChangedColumnWidths
orientation=
"horizontal"
>
false
</UserChangedColumnWidths>
<CurrentItem>
AddrDecoderWBApp.v
</CurrentItem>
<CurrentItem>
AddrDecoderWBApp.v
</CurrentItem>
</ItemView>
</ItemView>
...
@@ -58,17 +58,33 @@
...
@@ -58,17 +58,33 @@
<ClosedNodes>
<ClosedNodes>
<ClosedNodesVersion>
1
</ClosedNodesVersion>
<ClosedNodesVersion>
1
</ClosedNodesVersion>
<ClosedNode>
Design Utilities
</ClosedNode>
<ClosedNode>
Design Utilities
</ClosedNode>
<ClosedNode>
Implement Design
</ClosedNode>
<ClosedNode>
Implement Design/Map
</ClosedNode>
<ClosedNode>
Implement Design/Place
&
Route/Back-annotate Pin Locations
</ClosedNode>
<ClosedNode>
Implement Design/Place
&
Route/Generate IBIS Model
</ClosedNode>
<ClosedNode>
Implement Design/Place
&
Route/Generate Post-Place
&
Route Static Timing
</ClosedNode>
<ClosedNode>
Implement Design/Translate
</ClosedNode>
<ClosedNode>
Synthesize - XST
</ClosedNode>
<ClosedNode>
Synthesize - XST
</ClosedNode>
</ClosedNodes>
</ClosedNodes>
<SelectedItems>
<SelectedItems>
<<<<<<
< .mine
<SelectedItem
>
Generate Programming File
</SelectedItem>
=======
<SelectedItem>
Configure Target Device
</SelectedItem>
<SelectedItem>
Configure Target Device
</SelectedItem>
>>>>>>> .r43
</SelectedItems>
</SelectedItems>
<ScrollbarPosition
orientation=
"vertical"
>
0
</ScrollbarPosition>
<ScrollbarPosition
orientation=
"vertical"
>
0
</ScrollbarPosition>
<ScrollbarPosition
orientation=
"horizontal"
>
0
</ScrollbarPosition>
<ScrollbarPosition
orientation=
"horizontal"
>
0
</ScrollbarPosition>
<<<<<<
< .mine
<ViewHeaderState
orientation=
"horizontal"
>
000000ff00000000000000010000000100000000000000000000000000000000000000000000000191000000010000000100000000000000000000000064ffffffff000000810000000000000001000001910000000100000000
</ViewHeaderState>
=======
<ViewHeaderState
orientation=
"horizontal"
>
000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
</ViewHeaderState>
<ViewHeaderState
orientation=
"horizontal"
>
000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000
</ViewHeaderState>
>>>>>>> .r43
<UserChangedColumnWidths
orientation=
"horizontal"
>
false
</UserChangedColumnWidths>
<UserChangedColumnWidths
orientation=
"horizontal"
>
false
</UserChangedColumnWidths>
<<<<<<
< .mine
<CurrentItem
>
Generate Programming File
</CurrentItem>
=======
<CurrentItem>
Configure Target Device
</CurrentItem>
<CurrentItem>
Configure Target Device
</CurrentItem>
>>>>>>> .r43
</ItemView>
</ItemView>
<SourceProcessView>
000000ff00000000000000020000011b0000011b01000000050100000002
</SourceProcessView>
<SourceProcessView>
000000ff00000000000000020000011b0000011b01000000050100000002
</SourceProcessView>
<CurrentView>
Implementation
</CurrentView>
<CurrentView>
Implementation
</CurrentView>
...
...
trunk/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.xreport
View file @
77de1364
<?xml version='1.0' encoding='UTF-8'?>
<?xml version='1.0' encoding='UTF-8'?>
<report-views
version=
"2.0"
>
<report-views
version=
"2.0"
>
<header>
<header>
<<<<<<
< .mine
<DateModified
>
2010-12-20T12:22:48
</DateModified>
=======
<DateModified>
2010-12-20T14:11:35
</DateModified>
<DateModified>
2010-12-20T14:11:35
</DateModified>
>>>>>>> .r43
<ModuleName>
ApplicationFpga
</ModuleName>
<ModuleName>
ApplicationFpga
</ModuleName>
<SummaryTimeStamp>
Unknown
</SummaryTimeStamp>
<SummaryTimeStamp>
Unknown
</SummaryTimeStamp>
<SavedFilePath>
C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.xreport
</SavedFilePath>
<SavedFilePath>
C:/VFC_SVN/firmware/XilinxISE/ApplicationFpga/iseconfig/ApplicationFpga.xreport
</SavedFilePath>
...
...
trunk/hdl/design/SystemFpga.v
View file @
77de1364
...
@@ -373,9 +373,7 @@ Monostable i_ClearMonostable(
...
@@ -373,9 +373,7 @@ Monostable i_ClearMonostable(
assign
Si57xDivided
=
Si57xDivider_c
[
23
]
;
assign
Si57xDivided
=
Si57xDivider_c
[
23
]
;
always
@
(
posedge
Si57x_ik
)
Si57xDivider_c
<=
#
`dly
Si57xDivider_c
+
1'b1
;
always
@
(
posedge
Si57x_ik
)
Si57xDivider_c
<=
#
`dly
Si57xDivider_c
+
1'b1
;
always
@
(
posedge
Clk_k
)
<=
We
&&
Cyc
;
reg
Debug1
,
Debug2
,
Debug3
,
Debug4
;
reg
Debug1
,
Debug2
,
Debug3
Debug4
;
Monostable
i_Debug1Monostable
(
Monostable
i_Debug1Monostable
(
.
AsynchIn_ia
(
Debug1
)
,
.
AsynchIn_ia
(
Debug1
)
,
...
@@ -392,7 +390,7 @@ Monostable i_Debug3Monostable(
...
@@ -392,7 +390,7 @@ Monostable i_Debug3Monostable(
.
Clk_ik
(
Clk_k
)
,
.
Clk_ik
(
Clk_k
)
,
.
SynchOutput_oq
(
DebugForLed3
))
;
.
SynchOutput_oq
(
DebugForLed3
))
;
Monostable
i_Debug
3
Monostable
(
Monostable
i_Debug
4
Monostable
(
.
AsynchIn_ia
(
Debug4
)
,
.
AsynchIn_ia
(
Debug4
)
,
.
Clk_ik
(
Clk_k
)
,
.
Clk_ik
(
Clk_k
)
,
.
SynchOutput_oq
(
DebugForLed4
))
;
.
SynchOutput_oq
(
DebugForLed4
))
;
...
@@ -469,7 +467,7 @@ assign IntSource_b8[7:2] = GenericOutputReg1[7:2];
...
@@ -469,7 +467,7 @@ assign IntSource_b8[7:2] = GenericOutputReg1[7:2];
assign
IntSource_b8
[
1
]
=
SpiIdle
;
assign
IntSource_b8
[
1
]
=
SpiIdle
;
assign
IntSource_b8
[
0
]
=
SpiWaitingData
;
assign
IntSource_b8
[
0
]
=
SpiWaitingData
;
VmeInterfaceWB
i_VmeInterface
(
/*
VmeInterfaceWB i_VmeInterface(
.rst_i(Rst_rq),
.rst_i(Rst_rq),
.clk_i(Clk_k),
.clk_i(Clk_k),
.adr_o(Adr_b22),
.adr_o(Adr_b22),
...
@@ -501,7 +499,41 @@ VmeInterfaceWB i_VmeInterface(
...
@@ -501,7 +499,41 @@ VmeInterfaceWB i_VmeInterface(
.intlev_reg(InterrupLevel),
.intlev_reg(InterrupLevel),
.IrqVector_i(IntVector_b8),
.IrqVector_i(IntVector_b8),
.assert_interrupt(AssertInterrupt),
.assert_interrupt(AssertInterrupt),
.
clear_int
(
IntAcknowledged
))
;
.clear_int(IntAcknowledged)); */
VmeToWishBone
i_VmeInterface
(
.
Rst_irq
(
Rst_rq
)
,
.
Clk_ik
(
Clk_k
)
,
.
Adr_obq22
(
Adr_b22
)
,
.
Dat_obq32
(
DatMasterO_b32
)
,
.
Dat_ib32
(
DatMasterI_b32
)
,
.
We_oq
(
We
)
,
.
Cyc_oq
(
Cyc
)
,
.
Stb_oq
(
StbMaster
)
,
.
Ack_i
(
AckMaster
)
,
.
VmeGa_ib5
(
VmeGa_ib5n
)
,
.
VmeGap_i
(
VmeGaP_in
)
,
.
VmeAs_ia
(
VmeAs_in
)
,
.
VmeDs1_ia
(
VmeDs_inb2
[
1
])
,
.
VmeDs2_ia
(
VmeDs_inb2
[
2
])
,
.
VmeAm_ib6
(
VmeAm_ib6
)
,
.
VmeWr_in
(
VmeWrite_in
)
,
.
VmeDtAck_oqn
(
VmeDtAck_n
)
,
.
VmeLWord_i
(
VmeLword_io
)
,
.
VmeAddr_ib31
(
VmeA_iob31
)
,
.
VmeData_iozb32
(
VmeD_iob32
)
,
.
VmeDataOe_oq
(
VmeDOe
)
,
.
VmeDataDir_oq
(
VmeDDirVfcToVme_o
)
,
.
VmeIAckInn_in
(
VmeIackIn_in
)
,
.
VmeIAckn_in
(
VmeIack_in
)
,
.
VmeIAckOutn_oqn
(
VmeIackOut_on
)
,
.
VmeIrqn_oqnb7
(
VmeIrq_b7n
)
,
.
IntLevel_ib3
(
InterrupLevel
)
,
.
IrqVector_ib8
(
IntVector_b8
)
,
.
UseGa_i
(
UseGa_i
)
,
.
ManualAddress_ib5
(
ManualAddress_ib5
)
,
.
AssertInterrupt_i
(
AssertInterrupt
)
,
.
ClearInt_op
(
IntAcknowledged
))
;
InterruptManagerWB
i_InterruptManager
(
InterruptManagerWB
i_InterruptManager
(
.
Clk_ik
(
Clk_k
)
,
.
Clk_ik
(
Clk_k
)
,
...
...
trunk/simulation/makefile
View file @
77de1364
...
@@ -15,7 +15,7 @@ VerilogFiles+= ../hdl/design/Generic4InputRegs.v
...
@@ -15,7 +15,7 @@ VerilogFiles+= ../hdl/design/Generic4InputRegs.v
VerilogFiles
+=
../hdl/design/Monostable.v
VerilogFiles
+=
../hdl/design/Monostable.v
VerilogFiles
+=
../hdl/design/Debouncer.v
VerilogFiles
+=
../hdl/design/Debouncer.v
VerilogFiles
+=
../hdl/design/InterruptManagerWB.v
VerilogFiles
+=
../hdl/design/InterruptManagerWB.v
VerilogFiles
+=
../hdl/design/Vme
InterfaceWB
.v
VerilogFiles
+=
../hdl/design/Vme
ToWishBone
.v
VerilogFiles
+=
../hdl/design/Slv2SerWB.v
VerilogFiles
+=
../hdl/design/Slv2SerWB.v
VerilogFiles
+=
../hdl/design/SpiMasterWB.v
VerilogFiles
+=
../hdl/design/SpiMasterWB.v
# Application FPGA's modules
# Application FPGA's modules
...
...
trunk/software/mysim.py
View file @
77de1364
...
@@ -19,7 +19,7 @@ WaitSimulation('1000')
...
@@ -19,7 +19,7 @@ WaitSimulation('1000')
print
"Release: "
,
hex
(
MyBoard
.
ReleaseID
.
Read
())
print
"Release: "
,
hex
(
MyBoard
.
ReleaseID
.
Read
())
print
""
print
""
print
"
Enabling all the interrupts
"
print
"
Configuring the interrupt level and vector
"
MyBoard
.
ConfigureInterrupts
()
MyBoard
.
ConfigureInterrupts
()
print
"Int Config reg: "
,
hex
(
MyBoard
.
InterruptConfig
.
Read
())
print
"Int Config reg: "
,
hex
(
MyBoard
.
InterruptConfig
.
Read
())
print
""
print
""
...
...
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