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- 1 Direct Digital Synthesizer (DDS)
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- 3 Phase Locked Loop (PLL) chips for clock cleaning and
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redistribution to the FPGAs and the pluggable modules
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- 2 completely independent 72Mbit ZBT SRAMS
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- A 2Gbit DDR3
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- Large amount of on board mamory
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- 2 completely independent 72Mbit ZBT SRAMS
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- A 2Gbit DDR3
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- 2 SPI 128Mbit flash proms for multiboot S-FPGA powerup
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configuration, storage of the A-FPGA firmware or of critical
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data
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- Front panel connectivity
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- 2 Small Formfactor Pluggable (SFP)
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- 4 lemos configurable in all possible input/output combinations
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