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FMC TDC 1ns 5cha
Commits
d4e10faf
Commit
d4e10faf
authored
Nov 24, 2017
by
Tomasz Wlostowski
Committed by
Grzegorz Daniluk
Dec 11, 2017
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fmc_tdc_core: decrease timestamp FIFO size to 512 (so that it fits in the SPEC with WPRC v4.1)
parent
b2433b14
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Showing
5 changed files
with
187 additions
and
190 deletions
+187
-190
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+176
-170
timestamp_fifo.vhd
hdl/rtl/timestamp_fifo.vhd
+1
-1
timestamp_fifo_wb.vhd
hdl/rtl/timestamp_fifo_wb.vhd
+7
-16
timestamp_fifo_wbgen2_pkg.vhd
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
+2
-2
timestamp_fifo_wb.wb
hdl/rtl/wbgen/timestamp_fifo_wb.wb
+1
-1
No files found.
hdl/rtl/fmc_tdc_core.vhd
View file @
d4e10faf
...
...
@@ -158,7 +158,7 @@ entity fmc_tdc_core is
generic
(
g_span
:
integer
:
=
32
;
-- address span in bus interfaces
g_width
:
integer
:
=
32
;
-- data width in bus interfaces
g_simulation
:
boolean
:
=
FALSE
);
-- this generic is set to TRUE
g_simulation
:
boolean
:
=
false
);
-- this generic is set to TRUE
-- when instantiated in a test-bench
port
(
...
...
@@ -218,8 +218,8 @@ entity fmc_tdc_core is
-- WISHBONE bus interface with the GN4124/VME core for the configuration
-- of the TDC core (clk_sys)
cfg_slave_i
:
in
t_wishbone_slave_in
;
cfg_slave_o
:
out
t_wishbone_slave_out
;
cfg_slave_i
:
in
t_wishbone_slave_in
;
cfg_slave_o
:
out
t_wishbone_slave_out
;
timestamp_o
:
out
std_logic_vector
(
127
downto
0
);
timestamp_stb_o
:
out
std_logic
;
...
...
@@ -259,7 +259,7 @@ architecture rtl of fmc_tdc_core is
signal
acam_config
,
acam_config_rdbk
:
config_vector
;
signal
start_from_fpga
,
state_active_p
:
std_logic
;
-- retrigger control
signal
clk_i_cycles_offset
,
roll_over_nb
,
retrig_nb_offset
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
clk_i_cycles_offset
,
roll_over_nb
,
retrig_nb_offset
:
std_logic_vector
(
g_width
-1
downto
0
);
signal
local_utc_p
:
std_logic
;
signal
current_retrig_nb
:
std_logic_vector
(
g_width
-1
downto
0
);
-- UTC
...
...
@@ -272,7 +272,7 @@ architecture rtl of fmc_tdc_core is
signal
tdc_in_fpga_4
,
tdc_in_fpga_5
:
std_logic_vector
(
1
downto
0
);
signal
acam_tstamp_channel
:
std_logic_vector
(
2
downto
0
);
signal
rst_sys
:
std_logic
;
signal
rst_sys
:
std_logic
;
signal
timestamp_valid
:
std_logic
;
signal
timestamp
:
std_logic_vector
(
127
downto
0
);
...
...
@@ -287,7 +287,7 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC REGISTERS CONTROLLER --
---------------------------------------------------------------------------------------------------
reg_control_block
:
reg_ctrl
reg_control_block
:
reg_ctrl
generic
map
(
g_span
=>
g_span
,
g_width
=>
g_width
)
...
...
@@ -324,14 +324,20 @@ begin
starting_utc_o
=>
starting_utc
,
acam_inputs_en_o
=>
acam_inputs_en
,
start_phase_o
=>
window_delay
,
irq_tstamp_threshold_o
=>
irq_tstamp_threshold
,
irq_tstamp_threshold_o
=>
irq_tstamp_threshold
,
irq_time_threshold_o
=>
irq_time_threshold
,
send_dac_word_p_o
=>
send_dac_word_p_o
,
dac_word_o
=>
dac_word_o
,
one_hz_phase_o
=>
pulse_delay
);
irq_threshold_o
<=
irq_tstamp_threshold
(
9
downto
0
);
process
(
clk_tdc_i
)
begin
if
rising_edge
(
clk_tdc_i
)
then
irq_threshold_o
<=
irq_tstamp_threshold
(
9
downto
0
);
irq_timeout_o
<=
irq_time_threshold
(
9
downto
0
);
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...
...
@@ -339,7 +345,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- termination enable registers
term_enable_regs
:
process
(
clk_tdc_i
)
term_enable_regs
:
process
(
clk_tdc_i
)
begin
if
rising_edge
(
clk_tdc_i
)
then
if
rst_tdc_i
=
'1'
then
...
...
@@ -364,7 +370,7 @@ begin
---------------------------------------------------------------------------------------------------
-- LOCAL ONE HZ GENERATOR --
---------------------------------------------------------------------------------------------------
local_one_second_block
:
local_pps_gen
local_one_second_block
:
local_pps_gen
generic
map
(
g_width
=>
g_width
)
port
map
...
...
@@ -378,11 +384,11 @@ begin
local_utc_o
=>
local_utc
,
local_utc_p_o
=>
local_utc_p
);
clk_period
<=
f_pick
(
g_simulation
,
c_SIM_CLK_PERIOD
,
c_SYN_CLK_PERIOD
);
clk_period
<=
f_pick
(
g_simulation
,
c_SIM_CLK_PERIOD
,
c_SYN_CLK_PERIOD
);
---------------------------------------------------------------------------------------------------
-- ACAM TIMECONTROL INTERFACE --
---------------------------------------------------------------------------------------------------
acam_timing_block
:
acam_timecontrol_interface
acam_timing_block
:
acam_timecontrol_interface
port
map
(
err_flag_i
=>
err_flag_i
,
int_flag_i
=>
int_flag_i
,
...
...
@@ -405,7 +411,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
-- ACAM DATABUS INTERFACE --
---------------------------------------------------------------------------------------------------
acam_data_block
:
acam_databus_interface
acam_data_block
:
acam_databus_interface
port
map
(
ef1_i
=>
ef1_i
,
ef2_i
=>
ef2_i
,
...
...
@@ -433,7 +439,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
-- ACAM START RETRIGGER CONTROLLER --
---------------------------------------------------------------------------------------------------
start_retrigger_block
:
start_retrig_ctrl
start_retrigger_block
:
start_retrig_ctrl
generic
map
(
g_width
=>
g_width
)
port
map
...
...
@@ -451,9 +457,9 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
-- DATA ENGINE --
---------------------------------------------------------------------------------------------------
data_engine_block
:
data_engine
data_engine_block
:
data_engine
generic
map
(
g_simulation
=>
g_simulation
)
g_simulation
=>
g_simulation
)
port
map
(
acam_ack_i
=>
acm_ack
,
acam_dat_i
=>
acm_dat_r
,
...
...
@@ -493,7 +499,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
-- DATA FORMATTING --
---------------------------------------------------------------------------------------------------
data_formatting_block
:
data_formatting
data_formatting_block
:
data_formatting
port
map
(
clk_i
=>
clk_tdc_i
,
rst_i
=>
rst_tdc_i
,
...
...
@@ -524,7 +530,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
---------------------------------------------------------------------------------------------------
-- TDC LEDs --
---------------------------------------------------------------------------------------------------
TDCboard_leds
:
leds_manager
TDCboard_leds
:
leds_manager
generic
map
(
g_width
=>
32
,
g_simulation
=>
g_simulation
)
...
...
hdl/rtl/timestamp_fifo.vhd
View file @
d4e10faf
...
...
@@ -113,7 +113,7 @@ begin
regs_i
=>
regs_in
,
regs_o
=>
regs_out
);
buf_count
<=
unsigned
(
regs_out
.
fifo_wr_usedw_o
);
buf_count
<=
resize
(
unsigned
(
regs_out
.
fifo_wr_usedw_o
),
10
);
ts_match
<=
'1'
when
timestamp_valid_i
=
'1'
and
unsigned
(
timestamp_i
(
98
downto
96
))
=
g_channel
else
'0'
;
...
...
hdl/rtl/timestamp_fifo_wb.vhd
View file @
d4e10faf
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created :
Mon Apr 20 17:34:12 2015
-- Created :
Wed Sep 20 18:41:08 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
...
...
@@ -89,26 +89,16 @@ signal tsf_csr_rst_seq_sync2 : std_logic ;
signal
tsf_fifo_full_int
:
std_logic
;
signal
tsf_fifo_empty_int
:
std_logic
;
signal
tsf_fifo_clear_bus_int
:
std_logic
;
signal
tsf_fifo_usedw_int
:
std_logic_vector
(
9
downto
0
);
signal
tsf_fifo_usedw_int
:
std_logic_vector
(
8
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
3
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
...
...
@@ -310,7 +300,8 @@ begin
rddata_reg
(
16
)
<=
tsf_fifo_full_int
;
rddata_reg
(
17
)
<=
tsf_fifo_empty_int
;
rddata_reg
(
18
)
<=
'0'
;
rddata_reg
(
9
downto
0
)
<=
tsf_fifo_usedw_int
;
rddata_reg
(
8
downto
0
)
<=
tsf_fifo_usedw_int
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
...
...
@@ -353,9 +344,9 @@ begin
tsf_fifo_rst_n
<=
rst_n_i
and
(
not
tsf_fifo_clear_bus_int
);
tsf_fifo_INST
:
wbgen2_fifo_async
generic
map
(
g_size
=>
1024
,
g_size
=>
512
,
g_width
=>
128
,
g_usedw_size
=>
10
g_usedw_size
=>
9
)
port
map
(
wr_req_i
=>
regs_i
.
fifo_wr_req_i
,
...
...
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @
d4e10faf
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created :
Mon Apr 20 17:34:12 2015
-- Created :
Wed Sep 20 18:41:08 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
...
...
@@ -51,7 +51,7 @@ package tsf_wbgen2_pkg is
type
t_tsf_out_registers
is
record
fifo_wr_full_o
:
std_logic
;
fifo_wr_empty_o
:
std_logic
;
fifo_wr_usedw_o
:
std_logic_vector
(
9
downto
0
);
fifo_wr_usedw_o
:
std_logic_vector
(
8
downto
0
);
csr_last_valid_o
:
std_logic
;
csr_last_valid_load_o
:
std_logic
;
csr_rst_seq_o
:
std_logic
;
...
...
hdl/rtl/wbgen/timestamp_fifo_wb.wb
View file @
d4e10faf
...
...
@@ -9,7 +9,7 @@ peripheral {
-- TXTSU shared FIFO
fifo_reg {
size =
1024
; -- or more. We'll see :)
size =
512
; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "fifo";
name = "Timestamp FIFO";
...
...
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