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Commit a2393b49 authored by egousiou's avatar egousiou
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gnum_core folder cleanup 

git-svn-id: http://svn.ohwr.org/fmc-tdc@184 85dfdc96-de2c-444c-878d-45b388be74a9
parent 4a2e47ff
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hdl/ip_cores/gnum_core/genram_pkg.vhd deleted 100644 → 0
View file @ 4a2e47ff
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2011-05-11
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
end genram_pkg;
\ No newline at end of file
hdl/ip_cores/gnum_core/spartan6/Manifest.py 0 → 100644
View file @ a2393b49
files = ["gn4124_core.vhd",
"gn4124_core_pkg.vhd",
"l2p_ser.vhd",
"p2l_des.vhd",
"serdes_1_to_n_clk_pll_s2_diff.vhd",
"serdes_1_to_n_data_s2_se.vhd",
"serdes_n_to_1_s2_diff.vhd",
"serdes_n_to_1_s2_se.vhd",
"pulse_sync_rtl.vhd"]
hdl/ip_cores/gnum_core/gn4124_core.vhd → hdl/ip_cores/gnum_core/spartan6/gn4124_core.vhd
View file @ a2393b49
......@@ -9,7 +9,7 @@
-- authors: Simon Deprez (simon.deprez@cern.ch)
-- Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 31-08-2010///
-- date: 31-08-2010
--
-- version: 0.3
--
......@@ -97,7 +97,7 @@ entity gn4124_core is
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)------------pipeline
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
......@@ -247,6 +247,9 @@ architecture rtl of gn4124_core is
signal l2p_edb : std_logic;
signal l2p_edb_t : std_logic;
signal l2p_edb_t2 : std_logic;
signal tx_error_t2 : std_logic;
signal tx_error_t : std_logic;
signal tx_error : std_logic;
-------------------------------------------------------------
-- CSR wishbone master to arbiter
......@@ -630,6 +633,7 @@ begin
l2p_edb_o => l2p_edb,
l_wr_rdy_i => l_wr_rdy,
l2p_rdy_i => l2p_rdy,
tx_error_i => tx_error,
l2p_dma_clk_i => dma_clk_i,
l2p_dma_adr_o => l2p_dma_adr,
......@@ -764,6 +768,9 @@ begin
l2p_edb_o <= '0';
l2p_edb_t <= '0';
l2p_edb_t2 <= '0';
tx_error_t2 <= '0';
tx_error_t <= '0';
tx_error <= '0';
elsif rising_edge(sys_clk) then
-- must be checked before l2p_dma_master issues a master write
l_wr_rdy_t <= l_wr_rdy_i;
......@@ -780,6 +787,11 @@ begin
l2p_rdy_t2 <= l2p_rdy_t;
l2p_rdy <= l2p_rdy_t2;
-- when asserted, stop dma transfer. Should never be asserted under normal operation conditions!
tx_error_t <= tx_error_i;
tx_error_t2 <= tx_error_t;
tx_error <= tx_error_t2;
--assert when packet badly ends (e.g. dma abort)
l2p_edb_t <= l2p_edb;
l2p_edb_t2 <= l2p_edb_t;
......
hdl/ip_cores/gnum_core/gn4124_core_pkg.vhd → hdl/ip_cores/gnum_core/spartan6/gn4124_core_pkg.vhd
View file @ a2393b49
......@@ -397,6 +397,7 @@ package gn4124_core_pkg is
l2p_edb_o : out std_logic; -- Asserted when transfer is aborted
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Asserted when GN4124 is ready to receive master write
l2p_rdy_i : in std_logic; -- De-asserted to pause transfer already in progress
tx_error_i : in std_logic; -- Transmit Error
---------------------------------------------------------
-- DMA Interface (Pipelined Wishbone)
......
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