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FMC TDC 1ns 5cha
Commit 37f54785 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch '17_comments_cleanup' into 'master' 

headers cleanup and removal of old licenses

See merge request be-cem-edl/fec/hardware-modules/fmc-tdc-1ns-5cha!18
parents a7b887ce aab56b90
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hdl/rtl/acam_databus_interface.vhd
View file @ 37f54785
...@@ -2,38 +2,27 @@ ...@@ -2,38 +2,27 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- | -- Title : Acam databus interface
-- acam_databus_interface |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File acam_databus_interface.vhd | -- Description The unit interfaces with the ACAM chip pins for the configuration of the registers
-- | -- and the acquisition of the timestamps.
-- Description The unit interfaces with the ACAM chip pins for the configuration of the registers| -- The ACAM proprietary interface is converted to a WISHBONE classic interface, with
-- and the acquisition of the timestamps. | -- which the unit communicates with the data_engine unit.
-- The ACAM proprietary interface is converted to a WISHBONE classic interface, with | -- The WISHBONE master is implemented in the data_engine and the slave in this unit.
-- which the unit communicates with the data_engine unit. | --
-- The WISHBONE master is implemented in the data_engine and the slave in this unit. | -- ___________ ____________ ___________
-- | -- | |___WRn_______| | | |
-- ___________ ____________ ___________ | -- | |___RDn_______| |___stb______| |
-- | |___WRn_______| | | | | -- | |___CSn_______| |___cyc______| |
-- | |___RDn_______| |___stb______| | | -- | ACAM |___OEn_______| acam_ |___we_______| data_ |
-- | |___CSn_______| |___cyc______| | | -- | |___EF________| databus_ |___ack______| engine |
-- | ACAM |___OEn_______| acam_ |___we_______| data_ | | -- | | | interface |___adr______| |
-- | |___EF________| databus_ |___ack______| engine | | -- | |___ADR_______| |___datI_____| |
-- | | | interface |___adr______| | | -- | |___DatabusIO_| |___datO_____| |
-- | |___ADR_______| |___datI_____| | | -- |___________| |____________| |___________|
-- | |___DatabusIO_| |___datO_____| | | --
-- |___________| |____________| |___________| | --
-- |
-- |
----------------------------------------------/!\-------------------------------------------------| ----------------------------------------------/!\-------------------------------------------------|
-- In order for the core to be able to keep retreiving timestamps from the ACAM at the ACAM's | -- In order for the core to be able to keep retreiving timestamps from the ACAM at the ACAM's |
-- maximun speed (31.25 M timestamps/ sec), it needs to complete one retreival per | -- maximun speed (31.25 M timestamps/ sec), it needs to complete one retreival per |
...@@ -45,20 +34,6 @@ ...@@ -45,20 +34,6 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
-- Libraries & Packages -- Libraries & Packages
......
hdl/rtl/acam_timecontrol_interface.vhd
View file @ 37f54785
...@@ -2,37 +2,12 @@ ...@@ -2,37 +2,12 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- acam_timecontrol_interface |
-- |
---------------------------------------------------------------------------------------------------
-- File acam_timecontrol_interface.vhd |
-- |
-- Description Interface with the ACAM chip pins for control and timing. |
-- the start pulse is sent only once upon the activation of the acquisition, |
-- synchronously to the utc_p_i |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Acam timebase control
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description: Interface with the ACAM chip pins for control and timing.
-- ------------------------------------ | -- the start pulse is sent only once upon the activation of the acquisition,
-- This source file is free software; you can redistribute it and/or modify it under the terms of | -- synchronously to the utc_p_i
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -139,8 +114,8 @@ begin ...@@ -139,8 +114,8 @@ begin
stop_dis_o <= '1'; stop_dis_o <= '1';
else else
stop_dis_o <= stop_dis_d1; stop_dis_o <= stop_dis_d1;
end if; end if;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......
hdl/rtl/clks_rsts_manager.vhd
View file @ 37f54785
...@@ -2,54 +2,29 @@ ...@@ -2,54 +2,29 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- clks_rsts_manager |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File clks_rsts_manager.vhd | -- Title : clks_rsts_manager.vhd
-- |
-- Description Independent block that uses the clk_sys_i to parametrize the PLL and DAC on the |
-- TDC mezzanine. |
-- |
-- The PLL is programmed to generate a 125 MHz clock that arrives to the FPGA and |
-- is used by all the other units of the TDC core. |
-- It is also programmed to generate a 31.25 MHz clock which is the reference clock |
-- for the ACAM chip. |
-- The registers for programming the PLL are hard-coded in this unit. |
-- |
-- Regarding the DAC, it needs one 23-bit-long word for its configuration. This |
-- word along with the command for the configuration can be sent through the |
-- PCIe/VME interface, or automatically through the White Rabbit core. |
-- |
-- Note that the PLL needs to be configured on the falling edges of the sclk clock, |
-- whereas the DAC on the rising edges. |
-- |
-- The unit also generates of a global internal reset signal for the TDC core. |
-- This internal reset is triggered by a GN4124/VME interface reset or by a |
-- Power On Reset at startup and it remains asserted until the 125 MHz clock signal |
-- received from the PLL is stable (PLL lock). |
-- |
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description: Independent block that uses the clk_sys_i to parametrize the PLL and DAC on the
-- ------------------------------------ | -- TDC mezzanine
-- This source file is free software; you can redistribute it and/or modify it under the terms of | --
-- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- The PLL is programmed to generate a 125 MHz clock that arrives to the FPGA and
-- version 2.1 of the License, or (at your option) any later version. | -- is used by all the other units of the TDC core.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- It is also programmed to generate a 31.25 MHz clock which is the reference clock
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- for the ACAM chip.
-- See the GNU Lesser General Public License for more details. | -- The registers for programming the PLL are hard-coded in this unit.
-- You should have received a copy of the GNU Lesser General Public License along with this | --
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | -- Regarding the DAC, it needs one 23-bit-long word for its configuration. This
-- word along with the command for the configuration can be sent through the
-- PCIe/VME interface, or automatically through the White Rabbit core.
--
-- Note that the PLL needs to be configured on the falling edges of the sclk clock,
-- whereas the DAC on the rising edges.
--
-- The unit also generates of a global internal reset signal for the TDC core.
-- This internal reset is triggered by a GN4124/VME interface reset or by a
-- Power On Reset at startup and it remains asserted until the 125 MHz clock signal
-- received from the PLL is stable (PLL lock).
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
hdl/rtl/data_engine.vhd
View file @ 37f54785
...@@ -2,57 +2,31 @@ ...@@ -2,57 +2,31 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- data_engine |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File data_engine.vhd | -- Title : Data Engine
-- |
-- Description The unit is managing: |
-- o the timestamps' acquisition from the ACAM, |
-- o the writing of the ACAM configuration, |
-- o the reading back of the ACAM configuration. |
-- |
-- The signals: activate_acq, deactivate_acq, |
-- acam_wr_config, acam_rst |
-- acam_rdbk_config, acam_rdbk_status, acam_rdbk_ififo1, |
-- acam_rdbk_ififo2, acam_rdbk_start01 |
-- coming from the reg_ctrl unit determine the actions of this unit. |
-- |
-- o In acquisition mode (activate_acq = 1) the unit monitors permanently the empty |
-- flags (ef1, ef2) of the ACAM iFIFOs, reads timestamps accordingly and then |
-- sends them to the data_formatting unit for them to endup in the circular_buffer|
-- o To configure the ACAM or read back its configuration registers, the unit should|
-- be in inactive mode (deactivate_acq = 1). |
-- |
-- For all types of interactions with the ACAM chip, the unit acts as a WISHBONE |
-- master fetching/sending data from/to the ACAM interface. |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description The unit is managing:
--------------------------------------------------------------------------------------------------- -- o the timestamps' acquisition from the ACAM,
-- GNU LESSER GENERAL PUBLIC LICENSE | -- o the writing of the ACAM configuration,
-- ------------------------------------ | -- o the reading back of the ACAM configuration.
-- This source file is free software; you can redistribute it and/or modify it under the terms of | --
-- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- The signals: activate_acq, deactivate_acq,
-- version 2.1 of the License, or (at your option) any later version. | -- acam_wr_config, acam_rst
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- acam_rdbk_config, acam_rdbk_status, acam_rdbk_ififo1,
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- acam_rdbk_ififo2, acam_rdbk_start01
-- See the GNU Lesser General Public License for more details. | -- coming from the reg_ctrl unit determine the actions of this unit.
-- You should have received a copy of the GNU Lesser General Public License along with this | --
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | -- o In acquisition mode (activate_acq = 1) the unit monitors permanently the empty
-- flags (ef1, ef2) of the ACAM iFIFOs, reads timestamps accordingly and then
-- sends them to the data_formatting unit for them to endup in the fifos
-- o To configure the ACAM or read back its configuration registers, the unit should
-- be in inactive mode (deactivate_acq = 1).
--
-- For all types of interactions with the ACAM chip, the unit acts as a WISHBONE
-- master fetching/sending data from/to the ACAM interface.
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
-- Libraries & Packages -- Libraries & Packages
--================================================================================================= --=================================================================================================
...@@ -189,7 +163,7 @@ begin ...@@ -189,7 +163,7 @@ begin
acam_ef2_i, acam_wr_config_p_i, acam_ef2_i, acam_wr_config_p_i,
acam_rdbk_config_p_i, acam_rdbk_status_p_i, acam_ack_i, acam_rst_p_i, acam_rdbk_config_p_i, acam_rdbk_status_p_i, acam_ack_i, acam_rst_p_i,
acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i, acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i,
start_from_fpga_i, time_c, time_c_full_p) start_from_fpga_i, time_c, time_c_full_p)
begin begin
case engine_st is case engine_st is
...@@ -287,7 +261,7 @@ begin ...@@ -287,7 +261,7 @@ begin
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '1'; time_c_rst <= '1';
----------------------------------------------- -----------------------------------------------
if start_from_fpga_i = '1' then if start_from_fpga_i = '1' then
nxt_engine_st <= WAIT_FOR_START01; nxt_engine_st <= WAIT_FOR_START01;
...@@ -305,7 +279,7 @@ begin ...@@ -305,7 +279,7 @@ begin
acam_we <= '0'; acam_we <= '0';
time_c_en <= '1'; time_c_en <= '1';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if time_c = x"00004000" then if time_c = x"00004000" then
nxt_engine_st <= RD_START01; nxt_engine_st <= RD_START01;
...@@ -321,7 +295,7 @@ begin ...@@ -321,7 +295,7 @@ begin
acam_stb <= '1'; acam_stb <= '1';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '1'; time_c_en <= '1';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if acam_ack_i ='1' then if acam_ack_i ='1' then
...@@ -332,14 +306,14 @@ begin ...@@ -332,14 +306,14 @@ begin
when WAIT_UTC => -- wait until the next UTC comes; now the offsets of the start_retrig_ctrl unit are defined when WAIT_UTC => -- wait until the next UTC comes; now the offsets of the start_retrig_ctrl unit are defined
-- the ACAM is disabled during this period -- the ACAM is disabled during this period
----------------------------------------------- -----------------------------------------------
acam_cyc <= '0'; acam_cyc <= '0';
acam_stb <= '0'; acam_stb <= '0';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '1'; time_c_en <= '1';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if time_c_full_p ='1' then if time_c_full_p ='1' then
nxt_engine_st <= ACTIVE; nxt_engine_st <= ACTIVE;
...@@ -354,7 +328,7 @@ begin ...@@ -354,7 +328,7 @@ begin
acam_stb <= '0'; acam_stb <= '0';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '1'; time_c_rst <= '1';
----------------------------------------------- -----------------------------------------------
if deactivate_acq_p_i = '1' then if deactivate_acq_p_i = '1' then
...@@ -404,7 +378,8 @@ begin ...@@ -404,7 +378,8 @@ begin
acam_stb <= '1'; acam_stb <= '1';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; ----------------------------------------------- time_c_rst <= '0';
-----------------------------------------------
if deactivate_acq_p_i = '1' then if deactivate_acq_p_i = '1' then
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
...@@ -430,7 +405,7 @@ begin ...@@ -430,7 +405,7 @@ begin
acam_we <= '1'; acam_we <= '1';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if acam_ack_i = '1' and acam_adr = x"0E" then -- last address if acam_ack_i = '1' and acam_adr = x"0E" then -- last address
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
...@@ -446,7 +421,8 @@ begin ...@@ -446,7 +421,8 @@ begin
acam_stb <= '1'; acam_stb <= '1';
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; ----------------------------------------------- time_c_rst <= '0';
-----------------------------------------------
if acam_ack_i = '1' and acam_adr = x"0E" then -- last address if acam_ack_i = '1' and acam_adr = x"0E" then -- last address
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
...@@ -463,7 +439,7 @@ begin ...@@ -463,7 +439,7 @@ begin
acam_we <= '0'; acam_we <= '0';
time_c_en <= '0'; time_c_en <= '0';
time_c_rst <= '0'; time_c_rst <= '0';
----------------------------------------------- -----------------------------------------------
if acam_ack_i ='1' then if acam_ack_i ='1' then
nxt_engine_st <= INACTIVE; nxt_engine_st <= INACTIVE;
......
hdl/rtl/data_formatting.vhd
View file @ 37f54785
...@@ -2,40 +2,14 @@ ...@@ -2,40 +2,14 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- data_formatting |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File data_formatting.vhd | -- Title : Timestamp data formatting
-- |
-- Description Timestamp data formatting. |
-- Formats in a 128-bit word the |
-- o fine timestamps coming directly from the ACAM |
-- o plus the coarse timing internally measured in the core |
-- o plus the UTC time, coming from the WRabbit core if synchronization is |
-- established or from the internal local counter |
-- |
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description: Formats in a 128-bit word the
-- ------------------------------------ | -- o fine timestamps coming directly from the ACAM
-- This source file is free software; you can redistribute it and/or modify it under the terms of | -- o plus the coarse timing internally measured in the core
-- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- o plus the UTC time, coming from the WRabbit core if synchronization is
-- version 2.1 of the License, or (at your option) any later version. | -- established or from the internal local counter
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -154,10 +128,10 @@ begin ...@@ -154,10 +128,10 @@ begin
end process; end process;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Final Timestamp Formatting -- -- Final Timestamp Formatting
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- tstamp_formatting: slicing of the 32-bits word acam_tstamp1_i and acam_tstamp2_i as received -- tstamp_formatting: slicing of the 32-bits word acam_tstamp1_i and acam_tstamp2_i as received
-- from the data_engine unit, to construct the final timestamps to be stored in the circular_buffer -- from the data_engine unit, to construct the final timestamps
-- acam_tstamp1_i, acam_tstamp2_i have the following structure: -- acam_tstamp1_i, acam_tstamp2_i have the following structure:
-- [16:0] Stop-Start \ -- [16:0] Stop-Start \
...@@ -170,7 +144,7 @@ begin ...@@ -170,7 +144,7 @@ begin
-- [30] ef2 / -- [30] ef2 /
-- [31] ef1 / -- [31] ef1 /
-- The final timestamp written in the circular_buffer is a 128-bits word divided in four -- The final timestamp is a 128-bits word divided in four
-- 32-bits words with the following structure: -- 32-bits words with the following structure:
-- [31:0] Fine time to be added to the Coarse time: "00..00" & 16 bit Stop-Start; -- [31:0] Fine time to be added to the Coarse time: "00..00" & 16 bit Stop-Start;
-- each bit represents 81.03 ps -- each bit represents 81.03 ps
......
hdl/rtl/decr_counter.vhd
View file @ 37f54785
...@@ -2,42 +2,16 @@ ...@@ -2,42 +2,16 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File decr_counter.vhd |
-- |
-- Description Stop counter. Configurable "counter_top_i" and "width". |
-- "Current count value" and "counting done" signals available. |
-- "Counter done" signal asserted simultaneous to "current count value = 0". |
-- Countdown is launched each time "counter_load_i" is asserted for one clock tick. |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Free-running counter
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description Stop counter. Configurable "counter_top_i" and "width".
-- ------------------------------------ | -- "Current count value" and "counting done" signals available.
-- This source file is free software; you can redistribute it and/or modify it under the terms of | -- "Counter done" signal asserted simultaneous to "current count value = 0".
-- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- Countdown is launched each time "counter_load_i" is asserted for one clock tick.
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
-- Libraries & Packages -- Libraries & Packages
--================================================================================================= --=================================================================================================
...@@ -129,4 +103,4 @@ end architecture rtl; ...@@ -129,4 +103,4 @@ end architecture rtl;
--================================================================================================= --=================================================================================================
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
\ No newline at end of file
hdl/rtl/fmc_tdc_core.vhd
View file @ 37f54785
...@@ -2,111 +2,38 @@ ...@@ -2,111 +2,38 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- | -- Title : FMC TDC Core
-- fmc_tdc_core |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File fmc_tdc_core.vhd | -- Description The TDC core top level instantiates all the modules needed to provide to the
-- | -- GN4124/VME interface the timestamps generated in the ACAM chip.
-- Description The TDC core top level instantiates all the modules needed to provide to the |
-- GN4124/VME interface the timestamps generated in the ACAM chip. | -- A timestamp is referred to a UTC second;
-- | -- the coarse and fine time indicate with 81.03 ps resolution the amount of time
-- Figure 1 shows the architecture of this core. | -- passed after the last UTC second.
-- | -- If the White Rabbit synchronization has been established, the UTC time comes from
-- As the structure indicates, each timestamp is referred to a UTC second; the coarse| -- the White Rabbit core. Otherwise, the one_hz_gen unit is responsible for keeping
-- and fine time indicate with 81.03 ps resolution the amount of time passed after | -- the local UTC time relaying on the local TDC oscillator.
-- the last UTC second. | -- Timestamps are formatted to the structure above within the data_formatting unit
-- If the White Rabbit synchronization has been established, the UTC time comes from | --
-- the White Rabbit core. Otherwise, the one_hz_gen unit is responsible for keeping | -- In this application, the ACAM is used in I-Mode which provides unlimited measuring
-- the local UTC time relaying on the local TDC oscillator. | -- range with internal start retriggers. ACAM's counter of retriggers however is not
-- Timestamps are formatted to the structure above within the data_formatting unit & | -- large enough and there is the need to follow the retriggers inside the core; the
-- are stored in the circular_buffer, where the GN4124/VME core have direct access | -- start_retrig_ctrl unit is responsible for that.
-- | --
-- In this application, the ACAM is used in I-Mode which provides unlimited measuring| -- The acam_databus_interface implements the communication with the ACAM for its
-- range with internal start retriggers. ACAM's counter of retriggers however is not | -- configuration as well as for the timestamps retrieval.
-- large enough and there is the need to follow the retriggers inside the core; the | -- The acam_timecontrol_interface is mainly responsible for delivering to the ACAM
-- start_retrig_ctrl unit is responsible for that. | -- the start pulse, to which all timestamps are related.
-- | --
-- The acam_databus_interface implements the communication with the ACAM for its | -- The regs_ctrl implements the communication with the GN4124/VME interface for the
-- configuration as well as for the timestamps retrieval. | -- configuration of this core and of the ACAM.
-- The acam_timecontrol_interface is mainly responsible for delivering to the ACAM | -- The data_engine is managing the transferring of the configuration registers from
-- the start pulse, to which all timestamps are related. | -- the regs_ctrl to the ACAM chip; it is also managing the timestamps'
-- | -- acquisition from the ACAM chip, making it available to the data_formatting unit.
-- The regs_ctrl implements the communication with the GN4124/VME interface for the | --
-- configuration of this core and of the ACAM. | -- The clks_rsts_manager unit is providing 125 MHz clock and resets to the core.
-- The data_engine is managing the transferring of the configuration registers from |
-- the regs_ctrl to the ACAM chip; it is also managing the timestamps' |
-- acquisition from the ACAM chip, making it available to the data_formatting unit. |
-- |
-- The core is providing an interrupt in any of the following 3 cases: |
-- o accumulation of timestamps larger than the settable threshold |
-- o more time passed than the settable time threshold and >=1 timestamps arrived |
-- o error occurred in the ACAM chip |
-- |
-- The clks_rsts_manager unit is providing 125 MHz clock and resets to the core. |
-- _________________________________________________________ |
-- | | |
-- | ________________ ____________ | |
-- | | ____________ | | | ___________ | |
-- | | | | | | | | | | |
-- | | | ACAM time | | | | | irq gen | | |
-- | | | ctrl | | | | |___________| | |
-- | | |____________| | | | ___________ | ______ |
-- | | ____________ | | | | | | | | |
-- | | | | | | data | | | | | | |
-- | | | ACAM data | | | engine | | | | | | |
-- | | | ctrl | | | | | | | | | |
-- | | |____________| | | | | regs | | --> | | |
-- | |________________| | | | ctrl | | <-- | | |
-- ACAM <-- | fine time | | | | | | | |
-- chip --> | ____________ | | | | | | VME/ | |
-- | | | | | | | | |GN4124| |
-- | | start | | | | | | | core | |
-- | | retrig | | | | | | | | |
-- | |____________| | | | | | | | |
-- | coarse time | | | | | | | |
-- | | | | | | | | |
-- WRabbit --|------------------->|\ | | | | | | | |
-- UTC time | ____________ |O| |____________| |___________| | | | |
-- | | | |R| ___________ | | | |
-- | | 1 Hz gen |-->|/ ____________ | | | | | |
-- | |____________| | | | circular | | --> | | |
-- | local UTC time | data | | buffer | | <-- | | |
-- | | formating | | | | | | |
-- | _________________ |____________| |___________| | | | |
-- | |____TDC LEDs_____| | |______| |
-- | | |
-- |_________________________________________________________| |
-- TDC core |
-- _________________________________________________________ |
-- | | |
-- | clks_rsts_manager | |
-- |_________________________________________________________| |
-- |
-- Figure 1: TDC core architecture |
-- |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
......
hdl/rtl/fmc_tdc_direct_readout.vhd
View file @ 37f54785
...@@ -2,6 +2,10 @@ ...@@ -2,6 +2,10 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------------------
-- Title : Direct timestamps readout
---------------------------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 37f54785
...@@ -2,21 +2,10 @@ ...@@ -2,21 +2,10 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- | -- Title : TDC mezzanine
-- fmc_tdc_mezzanine |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File fmc_tdc_mezzanine.vhd | -- Description: The unit instantiates |
-- |
-- Description The unit instantiates |
-- o the TDC core | -- o the TDC core |
-- o the wrabbit_sync unit that is managing the White Rabbit synchronization and | -- o the wrabbit_sync unit that is managing the White Rabbit synchronization and |
-- control signals | -- control signals |
...@@ -67,18 +56,6 @@ ...@@ -67,18 +56,6 @@
-- | -- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
-- Libraries & Packages -- Libraries & Packages
...@@ -562,11 +539,6 @@ begin ...@@ -562,11 +539,6 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER -- -- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- IRQ sources
-- 0 -> number of accumulated timestamps reached threshold
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
gen_enable_eic : if g_USE_FIFO_READOUT or g_USE_DMA_READOUT generate gen_enable_eic : if g_USE_FIFO_READOUT or g_USE_DMA_READOUT generate
cmp_tdc_eic : entity work.tdc_eic cmp_tdc_eic : entity work.tdc_eic
port map ( port map (
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ 37f54785
...@@ -2,80 +2,10 @@ ...@@ -2,80 +2,10 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |SPEC TDC| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- fmc_tdc_wrapper |
-- |
---------------------------------------------------------------------------------------------------
-- Description Wrapper of the fmc_tdc_mezzanine core. It instantiates:
-- - the FMC-TDC mezzanine core for communication with the TDC board
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- The TDC mezzanine core is instantiated for the communication with the TDC board. | -- Title : TDC mezzanine wrapper
-- The TDC mezzanine core is running at 125 MHz. Like this the TDC core can keep up |
-- to speed with the maximum speed that the ACAM can be receiving timestamps. |
-- All the other cores are running at 62.5 MHz |
-- |
-- The 62.5MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of |
-- the SPEC board. |
-- The 125MHz clock for each TDC mezzanine comes from the PLL located on it. |
-- A clks_rsts_manager unit is responsible for automatically configuring the PLL upon|
-- the FPGA startup, using the 62.5MHz clock. The clks_rsts_manager is keeping the |
-- the TDC mezzanine core under reset until the respective PLL gets locked. |
-- |
-- For the TDC mezzanine core, the crossing from the 125 MHz world to the 62.5 MHz |
-- world takes place through the dedicated clock_crossing module. |
-- |
-- ___________________________________________________________________________ |
-- | | |
-- | ____________________________ ___ _____ | |
-- | | | | | | | | |
-- |------|------| WRabbit core, PHY, DAC | <----------> | | | | | |
-- \/ | |____________________________| | | | | | |
-- ________ | 62.5MHz | | | | | |
-- | | | ___________________ | | | | | |
-- | DAC |<->| | clks rsts manager | | | | G | | |
-- | PLL | |___________________| | | | | | |
-- | | | ____________________________ _______ | S | | N | | |
-- | | | | | | clk | | | | | | |
-- | ACAM |<->| | TDC mezzanine |-| cross |<--> | | | 4 | | |
-- |________| | |--|____________________________| |_______| | D | | | | |
-- TDC mezz | | 125MHz 62.5MHz | | | 1 | | |
-- | | ____________________________ | | | | | |
-- | |->| | | B | | 2 | | |
-- | | Vector Interrupt Controller| <----------> | | <--> | | | |
-- | |____________________________| | | | 4 | | |
-- | 62.5MHz | | | | | |
-- | ____________________________ | | | | | |
-- | | | | | | | | |
-- | | carrier_info | <----------> | | | | | |
-- | |____________________________| | | | | | |
-- | 62.5MHz |___| |_____| | |
-- | | |
-- | ______________________________________________ | |
-- SPEC LEDs <->| |___________________LEDs_______________________| | |
-- | | |
-- |___________________________________________________________________________| |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description: Wrapper of the fmc_tdc_mezzanine core
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
......
hdl/rtl/free_counter.vhd
View file @ 37f54785
...@@ -2,39 +2,13 @@ ...@@ -2,39 +2,13 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- free_counter |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File free_counter.vhd | -- Title : Free-running counter
-- |
-- Description Free running counter. Configurable "counter_top_i" and "width". |
-- "Current count value" and "counting done" signal available. |
-- "Counting done" signal asserted simultaneous to "current count value = 0". |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Description Free running counter. Configurable "counter_top_i" and "width".
-- "Current count value" and "counting done" signal available.
-- "Counting done" signal asserted simultaneous to "current count value = 0".
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
......
hdl/rtl/incr_counter.vhd
View file @ 37f54785
...@@ -2,41 +2,16 @@ ...@@ -2,41 +2,16 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- | -- Title : incriment counter
-- incr_counter |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File incr_counter.vhd | -- Description: Stop counter. Configurable "counter_top_i" and "width".
-- | -- "Current count value" and "counting done" signals available.
-- Description Stop counter. Configurable "counter_top_i" and "width". | -- "Counting done" signal asserted simultaneous to"current count value=counter_top_i"
-- "Current count value" and "counting done" signals available. | -- Needs a rst_i to restart.
-- "Counting done" signal asserted simultaneous to"current count value=counter_top_i"|
-- Needs a rst_i to restart. |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
-- Libraries & Packages -- Libraries & Packages
......
hdl/rtl/leds_manager.vhd
View file @ 37f54785
...@@ -2,48 +2,23 @@ ...@@ -2,48 +2,23 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- leds_manager |
-- |
---------------------------------------------------------------------------------------------------
-- File leds_manager.vhd |
-- |
-- Description Generation of the signals that drive the LEDs on the TDC mezzanine. |
-- There are 6 LEDs on the front panel of the TDC mezzanine board: |
-- ______ |
-- | | |
-- | O O | 1, 2 |
-- | O O | 3, 4 |
-- | O O | 5, STA |
-- |______| |
-- |
-- TDC LEDs: blink upon the generation of a valid timestamp |
-- Inverted blinking (LED permanently ON without pulses in the input) indicates the |
-- 50 Ohm termination is active on the channel. |
-- |
-- TDC LED STA orange:division of the 125 MHz clock; one hz pulses |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : LEDs manager
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description: Generation of the signals that drive the LEDs on the TDC mezzanine.
-- ------------------------------------ | -- There are 6 LEDs on the front panel of the TDC mezzanine board:
-- This source file is free software; you can redistribute it and/or modify it under the terms of | -- ______
-- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- | |
-- version 2.1 of the License, or (at your option) any later version. | -- | O O | 1, 2
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- | O O | 3, 4
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- | O O | 5, STA
-- See the GNU Lesser General Public License for more details. | -- |______|
-- You should have received a copy of the GNU Lesser General Public License along with this | --
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | -- TDC LEDs: blink upon the generation of a valid timestamp
-- Inverted blinking (LED permanently ON without pulses in the input) indicates the
-- 50 Ohm termination is active on the channel
--
-- TDC LED STA orange:division of the 125 MHz clock; one hz pulses
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
hdl/rtl/local_pps_gen.vhd
View file @ 37f54785
...@@ -2,38 +2,13 @@ ...@@ -2,38 +2,13 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- | -- Title : Local PPS generator
-- local_pps_gen |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File local_pps_gen.vhd | -- Description: Generates one pulse every second synchronously with the ACAM reference clock
-- | -- It also keeps track of the UTC time based on the local clock.
-- Description Generates one pulse every second synchronously with the ACAM reference clock. | -- If there is no White Rabbit synchronization, this unit is the source of UTC timing
-- It also keeps track of the UTC time based on the local clock. |
-- If there is no White Rabbit synchronization, this unit is the source of UTC timing|
-- in the design. -- in the design.
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
hdl/rtl/reg_ctrl.vhd
View file @ 37f54785
...@@ -2,21 +2,9 @@ ...@@ -2,21 +2,9 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- reg_ctrl |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File reg_ctrl.vhd | -- Title : Register control
-- | --------------------------------------------------------------------------------------------------- -- Description Interfaces with the GN4124/VME core for the configuration of the ACAM chip and of |
-- Description Interfaces with the GN4124/VME core for the configuration of the ACAM chip and of |
-- the TDC core. Data transfers take place between the GN4124/VME interface and | -- the TDC core. Data transfers take place between the GN4124/VME interface and |
-- locally the TDC core. The unit implements a WISHBONE slave. | -- locally the TDC core. The unit implements a WISHBONE slave. |
-- | -- |
...@@ -37,19 +25,6 @@ ...@@ -37,19 +25,6 @@
-- | -- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
......
hdl/rtl/reg_ctrl_pkg.vhd
View file @ 37f54785
...@@ -2,11 +2,9 @@ ...@@ -2,11 +2,9 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Address constants of the reg_ctrl unit -- Title : Address constants of the Register Control unit
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File : reg_ctrl_pkg.vhd
---------------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
......
hdl/rtl/start_retrig_ctrl.vhd
View file @ 37f54785
...@@ -2,21 +2,11 @@ ...@@ -2,21 +2,11 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- | -- Title : TDC core pkg
-- start_retrig_ctrl |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File start_retrig_ctrl.vhd | ---------------------------------------------------------------------------------------------------
-- | -- Description: The unit provides the main components for the calculation of the "Coarse time" of |
-- Description The unit provides the main components for the calculation of the "Coarse time" of |
-- the final timestamps. These components are sent to the data_formatting unit where | -- the final timestamps. These components are sent to the data_formatting unit where |
-- the actual Coarse time calculation takes place. | -- the actual Coarse time calculation takes place. |
-- | -- |
...@@ -94,18 +84,6 @@ ...@@ -94,18 +84,6 @@
-- | -- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
......
hdl/rtl/tdc_core_pkg.vhd
View file @ 37f54785
...@@ -2,39 +2,18 @@ ...@@ -2,39 +2,18 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- tdc_core_pkg |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File tdc_core_pkg.vhd | -- Title : TDC core pkg
-- |
-- Description Package containing core wide constants and components |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description: Package containing core wide constants and components
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
-- Libraries & Packages -- Libraries & Packages
--================================================================================================= --=================================================================================================
...@@ -605,11 +584,11 @@ package tdc_core_pkg is ...@@ -605,11 +584,11 @@ package tdc_core_pkg is
clk_i : in std_logic; clk_i : in std_logic;
activate_acq_p_i : in std_logic; activate_acq_p_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
state_active_p_i : in std_logic; state_active_p_i : in std_logic;
deactivate_acq_p_i : in std_logic; deactivate_acq_p_i : in std_logic;
---------------------------------------------------------------------- ----------------------------------------------------------------------
start_from_fpga_o : out std_logic; start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
acam_errflag_r_edge_p_o : out std_logic; acam_errflag_r_edge_p_o : out std_logic;
acam_errflag_f_edge_p_o : out std_logic; acam_errflag_f_edge_p_o : out std_logic;
acam_intflag_f_edge_p_o : out std_logic); acam_intflag_f_edge_p_o : out std_logic);
...@@ -841,4 +820,3 @@ end tdc_core_pkg; ...@@ -841,4 +820,3 @@ end tdc_core_pkg;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
hdl/rtl/tdc_dma_channel.vhd
View file @ 37f54785
...@@ -2,6 +2,10 @@ ...@@ -2,6 +2,10 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
-------------------------------------------------------------------------------
-- Title : DMA channel
-------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.STD_LOGIC_1164.all; use ieee.STD_LOGIC_1164.all;
......
hdl/rtl/tdc_dma_engine.vhd
View file @ 37f54785
...@@ -2,6 +2,10 @@ ...@@ -2,6 +2,10 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------------------
-- Title : DMA engine
---------------------------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.STD_LOGIC_1164.all; use ieee.STD_LOGIC_1164.all;
......
hdl/rtl/tdc_ts_addsub.vhd
View file @ 37f54785
...@@ -2,18 +2,10 @@ ...@@ -2,18 +2,10 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Pipelined timestamp subtractor -- Title : Pipelined timestamp adder (adds q = a + b, b can be NEGATIVE)
-- Project : FMC TDC Core ---------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File : tdc_ts_sub.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2019-09-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pipelined timestamp adder with re-normalization of the result. -- Description: Pipelined timestamp adder with re-normalization of the result.
-- Adds a to b, producing normalized timestamp q. A timestmap is normalized when -- Adds a to b, producing normalized timestamp q. A timestmap is normalized when
-- the 0 <= frac < g_frac_range, 0 <= coarse <= g_coarse_range-1 and utc >= 0. -- the 0 <= frac < g_frac_range, 0 <= coarse <= g_coarse_range-1 and utc >= 0.
...@@ -23,25 +15,7 @@ ...@@ -23,25 +15,7 @@
-- 2. 0 <= a_frac < g_frac_range -- 2. 0 <= a_frac < g_frac_range
-- 3. -g_frac_range / 2 <= b_frac < g_frac_range / 2 -- 3. -g_frac_range / 2 <= b_frac < g_frac_range / 2
-- 4. -g_coarse_range+1 <= (a_coarse + b_coarse) <= 3*g_coarse_range-1 -- 4. -g_coarse_range+1 <= (a_coarse + b_coarse) <= 3*g_coarse_range-1
------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
library ieee; library ieee;
......
hdl/rtl/tdc_ts_sub.vhd
View file @ 37f54785
...@@ -2,18 +2,9 @@ ...@@ -2,18 +2,9 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Title : Pipelined timestamp subtractor -- Title : Pipelined timestamp subtractor (subtracts q = b - a)
-- Project : FMC TDC Core ---------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : tdc_ts_sub.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-29
-- Last update: 2018-08-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pipelined timestamp adder with re-normalization of the result. -- Description: Pipelined timestamp adder with re-normalization of the result.
-- Adds a to b, producing normalized timestamp q. A timestmap is normalized when -- Adds a to b, producing normalized timestamp q. A timestmap is normalized when
-- the 0 <= frac < 2**g_frac_bits, 0 <= coarse <= g_coarse_range-1 and utc >= 0. -- the 0 <= frac < 2**g_frac_bits, 0 <= coarse <= g_coarse_range-1 and utc >= 0.
...@@ -21,25 +12,7 @@ ...@@ -21,25 +12,7 @@
-- following constraints: -- following constraints:
-- 1. 0 <= (a/b)_frac_i <= 2**g_frac_bits-1 -- 1. 0 <= (a/b)_frac_i <= 2**g_frac_bits-1
-- 2. -g_coarse_range+1 <= (a_coarse_i + b_coarse_i) <= 3*g_coarse_range-1 -- 2. -g_coarse_range+1 <= (a_coarse_i + b_coarse_i) <= 3*g_coarse_range-1
------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
library ieee; library ieee;
......
hdl/rtl/timestamp_convert_filter.vhd
View file @ 37f54785
...@@ -2,6 +2,9 @@ ...@@ -2,6 +2,9 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
---------------------------------------------------------------------------------------------------
-- Title : Timestamp converter and filter
---------------------------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.STD_LOGIC_1164.all; use ieee.STD_LOGIC_1164.all;
......
hdl/rtl/timestamp_fifo.vhd
View file @ 37f54785
...@@ -2,25 +2,9 @@ ...@@ -2,25 +2,9 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________ -------------------------------------------------------------------------------
-- | -- Title : Timestamp FIFO
-- |TDC core| | -------------------------------------------------------------------------------
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
......
hdl/rtl/wrabbit_sync.vhd
View file @ 37f54785
...@@ -3,45 +3,12 @@ ...@@ -3,45 +3,12 @@
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Title : Counter Sync signal generator -- Title : WR synch
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- File : wrabbit_sync.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-08-09
-- Platform : FPGA-generic
-- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: Generates the internal time base used to synchronize the TDC -- Description: Generates the internal time base used to synchronize the TDC
-- and programmable pulse generators to an internal or WR-provided timescale. -- and programmable pulse generators to an internal or WR-provided timescale.
-- Also interfaces the FD core with an optional White Rabbit PTP core. -- Also interfaces the TDC core with an optional White Rabbit PTP core.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-08-24 1.0 twlostow Created
-- 2012-02-16 1.1 twlostow built-in WR sync FSM (untested)
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
library ieee; library ieee;
......
hdl/top/spec/wr_spec_tdc.vhd
View file @ 37f54785
...@@ -2,92 +2,29 @@ ...@@ -2,92 +2,29 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |SPEC TDC| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wr_spec_tdc |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File wr_spec_tdc.vhd | -- Title : TDC on SPEC with WR support
-- |
-- Description TDC top level with White Rabbit support for a SPEC carrier. |
-- Figure 1 shows the architecture of the unit. |
-- |
-- For the communication with the PCIe, the ohwr.org GN4124 core is instantiated. |
-- |
-- The TDC mezzanine core is instantiated for the communication with the TDC board. |
-- The White Rabbit core is controlling the DAC on each TDC mezzanine; the DAC is in |
-- turn controlling the PLL frequency. Once the PLL is synchronized to White Rabbit, |
-- the TDC core starts using the White Rabbit UTC for the timestamps calculations. |
-- The VIC core is forwarding the interrupts coming from the TDC mezzanine core to |
-- the GN4124 core. |
-- The carrier_info module provides general information on the SPEC PCB version, PLLs|
-- locking state etc. |
-- All the cores communicate with the GN4124 core through the SDB crossbar. The SDB |
-- crossbar is responsible for managing the acess to the GN4124 core. |
-- |
-- The TDC mezzanine core is running at 125 MHz. Like this the TDC core can keep up |
-- to speed with the maximum speed that the ACAM can be receiving timestamps. |
-- All the other cores (White Rabbit, VIC, carrier csr, 1-Wire as well as the GN4124 |
-- WISHBONE) are running at 62.5 MHz |
-- |
-- The 62.5MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of |
-- the SPEC board. |
-- The 125MHz clock for each TDC mezzanine comes from the PLL located on it. |
-- A clks_rsts_manager unit is responsible for automatically configuring the PLL upon|
-- the FPGA startup, using the 62.5MHz clock. The clks_rsts_manager is keeping the |
-- the TDC mezzanine core under reset until the respective PLL gets locked. |
-- |
-- ___________________________________________________________________________ |
-- | | |
-- | ____________________________ ___ _____ | |
-- | | | | | | | | |
-- |------|------| WRabbit core, PHY, DAC | <----------> | | | | | |
-- \/ | |____________________________| | | | | | |
-- ________ | 62.5MHz | | | | | |
-- | | | | | | | | |
-- | DAC |<->| | | | G | | |
-- | PLL | | | | | | |
-- | | | ____________________________ | S | | N | | |
-- | | | | | | | | | | |
-- | ACAM |<->|------| TDC wrapper |<------------> | | | 4 | | |
-- |________| | |--|____________________________| | D | | | | |
-- TDC mezz | | 62.5MHz | | | 1 | | |
-- | | ____________________________ | | | | | |
-- | |->| | | B | | 2 | | |
-- | | Vector Interrupt Controller| <----------> | | <--> | | | |
-- | |____________________________| | | | 4 | | |
-- | 62.5MHz | | | | | |
-- | ____________________________ | | | | | |
-- | | | | | | | | |
-- | | carrier_info | <----------> | | | | | |
-- | |____________________________| | | | | | |
-- | 62.5MHz |___| |_____| | |
-- | | |
-- | ______________________________________________ | |
-- SPEC LEDs <->| |___________________LEDs_______________________| | |
-- | | |
-- |___________________________________________________________________________| |
-- |
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE | -- Description: TDC top level with White Rabbit support for a SPEC carrier.
-- ------------------------------------ | --
-- This source file is free software; you can redistribute it and/or modify it under the terms of | -- The TDC mezzanine core is instantiated for the communication with the TDC board.
-- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- The spec_base_wr provides White Rabbit and host communication.
-- version 2.1 of the License, or (at your option) any later version. | -- Readout interface: DMA or per-channel FIFOs
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | --
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- Rising-edges belonging to pulses <96 ns are timestamped;
-- See the GNU Lesser General Public License for more details. | -- pulses < 96ns and falling edge timestamps are ignored
-- You should have received a copy of the GNU Lesser General Public License along with this | --
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | -- The TDC mezzanine core is running at 125 MHz. Like this the TDC core can keep up
-- to speed with the maximum speed that the ACAM can be receiving timestamps.
-- All the other cores (White Rabbit, VIC, carrier csr, 1-Wire as well as the GN4124
-- WISHBONE) are running at 62.5 MHz
--
-- The 62.5MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of
-- the SPEC board.
-- The 125MHz clock for each TDC mezzanine comes from the PLL located on it.
-- A clks_rsts_manager unit is responsible for automatically configuring the PLL upon
-- the FPGA startup, using the 62.5MHz clock. The clks_rsts_manager is keeping the
-- the TDC mezzanine core under reset until the respective PLL gets locked.
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
library IEEE; library IEEE;
......
hdl/top/svec/wr_svec_tdc.vhd
View file @ 37f54785
...@@ -2,104 +2,31 @@ ...@@ -2,104 +2,31 @@
-- --
-- SPDX-License-Identifier: CERN-OHL-W-2.0+ -- SPDX-License-Identifier: CERN-OHL-W-2.0+
--_________________________________________________________________________________________________
-- |
-- |SVEC TDC| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- | -- Title : TDC on SVEC with WR support
-- wr_svec_tdc |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File wr_svec_tdc.vhd | -- Description: Two TDC mezzanine cores are instantiated, for the boards on FMC1 and FMC2
-- | -- The svec_base_wr provides White Rabbit and host communication.
-- Description TDC top level for SVEC with White Rabbit. | -- Readout interface: per-channel FIFOs
-- Figure 1 shows the architecture of this unit. | --
-- o Two TDC mezzanine cores are instantiated, for the boards on FMC1 and FMC2 | -- Rising-edges belonging to pulses <96 ns are timestamped;
-- o The White Rabbit core is controlling the DAC on each TDC mezzanine; the DAC | -- pulses < 96ns and falling edge timestamps are ignored
-- is in turn controlling the PLL frequency. Once the PLL is synchronized to | --
-- White Rabbit, the TDC core starts using the White Rabbit UTC for the |
-- timestamps calculations. |
-- o The VIC is managing the interrupts coming from both TDC EIC cores |
-- o The carrier_info module provides general information on the SVEC PCB version, |
-- PLLs locking state etc |
-- All these cores communicate with the VME core through the WISHBONE. |
-- The SDB crossbar is mapping the different slaves into the WISHBONE address space. |
-- |
-- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores -- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores
-- internally operate at 125 MHz, but the wishbone bus works still -- internally operate at 125 MHz, but the wishbone bus works still
-- at system-wide 62.5 MHz clock. -- at system-wide 62.5 MHz clock.
-- | --
-- The 62.5 MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of| -- The 62.5 MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of
-- the SVEC board. | -- the SVEC board.
-- | --
-- The 125 MHz clock for each TDC mezzanine comes from the PLL located on it. | -- The 125 MHz clock for each TDC mezzanine comes from the PLL located on it.
-- | --
-- Upon powering up of the FPGA as well as after a VME reset, the whole logic gets | -- Upon powering up of the FPGA as well as after a VME reset, the whole logic gets
-- reset (FMC1 125 MHz, FMC2 125 MHz and 62.5 MHz). This also triggers a | -- reset (FMC1 125 MHz, FMC2 125 MHz and 62.5 MHz). This also triggers a
-- reprogramming of the mezzanines' PLL through the clks_rsts_manager units. | -- reprogramming of the mezzanines' PLL through the clks_rsts_manager units.
-- An extra software reset is implemented for the TDC mezzanine cores, using the | -- An extra software reset is implemented for the TDC mezzanine cores, using the
-- reset bits of the carrier_info core. Such a reset also triggers the reprogramming | -- reset bits of the carrier_info core. Such a reset also triggers the reprogramming
-- of the mezzanines' PLL. | -- of the mezzanines' PLL.
-- |
-- __________________________________________________________________ |
-- | | |
-- | ____________________________ | |
-- | | | ___ | |
-- | |---| WRabbit core, PHY, DAC |\ | | | |
-- | | |____________________________| \ | | | |
-- | 62.5MHz \ | | | |
-- | | ____________________________ \| | _____ | |
-- | | | | | | | | | |
-- | |---| | | | | | | |
-- | | | | | | | | | |
-- FMC1 | | | TDC mezzanine 1 |\ | | | | | |
-- | | | wrapper | \ | | | | | |
-- | | | | \ | | | | | |
-- | |---| | \ | | | | | |
-- | | |____________________________| \| | | | | |
-- | | | | | | | |
-- | | ____________________________ | | | | | |
-- | | | | | | | | | |
-- | | | | | | | | | |
-- | |---| | | S | | V | | |
-- FMC2 | | | TDC mezzanine 2 | ---- | | | | | |
-- | | | wrapper | | | | | | |
-- | | | | | | | | | |
-- | |---| | | | | | | |
-- | |____________________________| | D | <--> | M | | |
-- | | | | | | |
-- | ____________________________ | | | | | |
-- | | | | | | | | |
-- | | VIC | ---- | B | | E | | |
-- | |____________________________| | | | | | |
-- | 62.5MHz | | | | | |
-- | ____________________________ / | | | | | |
-- | | | / | | | | | |
-- | | carrier_info | / | | | | | |
-- | |____________________________| | | | | | |
-- | 62.5MHz |___| |_____| | |
-- | 62.5MHZ 62.5MHz | |
-- | ______________________________________________ | |
-- | |___________________LEDs_______________________| | |
-- | | |
-- |__________________________________________________________________| |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
......
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