rtl: fix handling of no fifo_readout

The block cannot be completly removed as it defines some registers that are still used even when the fifos are not present.

rtl: fix handling of no fifo_readout
The block cannot be completly removed as it defines some registers that are still used even when the fifos are not present.
07b91e04 · Tristan Gingold · e4906dab · 07b91e04 · 07b91e04
Commit 07b91e04 authored Oct 16, 2020 by Tristan Gingold
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Showing with 129 additions and 115 deletions

fmc_tdc_mezzanine.vhd hdl/rtl/fmc_tdc_mezzanine.vhd +2 -4

timestamp_fifo.vhd hdl/rtl/timestamp_fifo.vhd +127 -111

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--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
@@ -386,10 +386,10 @@ begin
 --                                           x5 FIFOS                                            --
 ---------------------------------------------------------------------------------------------------
 -- A FIFO with the timestamps of each channel
-  gen_enable_fifo_readout : if g_USE_FIFO_READOUT generate
  gen_fifos : for i in 0 to 4 generate
    U_TheFifo : entity work.timestamp_fifo
        generic map (
+          g_enable => g_USE_FIFO_READOUT,
          g_channel => i)
        port map (
          clk_sys_i         => clk_sys_i,
@@ -409,8 +409,6 @@ begin

      timestamp_stb(i) <= tdc_timestamp_valid_p(i);
  end generate gen_fifos;
-  end generate gen_enable_fifo_readout;
-

      -- generic map (
        -- g_USE_FIFO_READOUT => g_USE_FIFO_READOUT)

--- a/hdl/rtl/timestamp_fifo.vhd
+++ b/hdl/rtl/timestamp_fifo.vhd
@@ -29,6 +29,7 @@ use work.gencores_pkg.all;

 entity timestamp_fifo is
  generic (
+    g_enable : boolean;
    g_channel : integer
    );
  port (
@@ -63,10 +64,8 @@ architecture rtl of timestamp_fifo is
  signal buf_irq_int : std_logic;
  signal buf_count   : unsigned(9 downto 0);

-  signal last_ts    : std_logic_vector(127 downto 0);
  signal regs_in    : t_tsf_in_registers;
  signal regs_out   : t_tsf_out_registers;
-  signal channel_id : std_logic_vector(2 downto 0);

  signal ts_match : std_logic;

@@ -83,14 +82,25 @@ architecture rtl of timestamp_fifo is

 begin

+  --  Registers decoder
+  U_WB_Slave : entity work.timestamp_fifo_wb
+    port map (
+      rst_n_i   => rst_sys_n_i,
+      clk_sys_i => clk_sys_i,
+      slave_i   => slave_i,
+      slave_o   => slave_o,
+      regs_i    => regs_in,
+      regs_o    => regs_out);

-  
+  --  Common parts
  ts_offset_o.tai <= regs_out.offset1_o;
  ts_offset_o.coarse <= regs_out.offset2_o;
  ts_offset_o.frac <= regs_out.offset3_o(11 downto 0);
  reset_seq_o <= regs_out.csr_rst_seq_o;
  raw_enable_o <= regs_out.csr_raw_mode_o;

+  --  Enable the fifo part only if the fifo readout is enabled.
+  gen_fifos: if g_enable generate
    timestamp_with_seq(31 downto 0)    <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
    timestamp_with_seq(63 downto 32)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
    timestamp_with_seq(95 downto 64)   <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).frac), 32));
@@ -98,16 +108,6 @@ begin
    timestamp_with_seq(99)            <= timestamp_i(g_channel).slope;
    timestamp_with_seq(127 downto 100) <= timestamp_i(g_channel).seq(27 downto 0);

-
-  U_WB_Slave : entity work.timestamp_fifo_wb
-    port map (
-      rst_n_i   => rst_sys_n_i,
-      clk_sys_i => clk_sys_i,
-      slave_i   => slave_i,
-      slave_o   => slave_o,
-      regs_i    => regs_in,
-      regs_o    => regs_out);
-
    buf_count <= resize(unsigned(regs_out.fifo_wr_usedw_o), 10);

    ts_match <= timestamp_valid_i(g_channel);
@@ -219,5 +219,21 @@ begin
    end process;

    irq_o <= buf_irq_int;
+  end generate;
+
+  --  Disable the fifo part.  Unfortunately even when the fifos are disabled we still need a few
+  --  register of the map.
+  gen_no_fifos: if not g_enable generate
+    regs_in.fifo_wr_req_i <= '0';
+    irq_o <= '0';
+    regs_in.fifo_ts0_i <= (others => '0');
+    regs_in.fifo_ts1_i <= (others => '0');
+    regs_in.fifo_ts2_i <= (others => '0');
+    regs_in.fifo_ts3_i <= (others => '0');
+    regs_in.delta1_i <= (others => '0');
+    regs_in.delta2_i <= (others => '0');
+    regs_in.delta3_i <= (others => '0');
+    regs_in.csr_delta_ready_i <= '0';
+  end generate;

 end rtl;