- 07 Sep, 2018 4 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Tomasz Wlostowski authored
a crude performance & validity testing tool for the DMA readout Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>
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Tomasz Wlostowski authored
- FIFO readout - offset is applied in hardware - delta is calculated in hardware - add RAW mode readout (no TS post-processing) Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch> Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 04 Sep, 2018 1 commit
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 30 Aug, 2018 3 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
With this patch I try to improve performances by using interrupts and the ZIO dma API. This allows me to program different blocks form different channel at the same time Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 29 Aug, 2018 4 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
bugfixes
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Tomasz Wlostowski authored
- needs new bitstream (28 August onwards) - fixed scatter list allocation (needs one more entry for the start item) - fixed DMA direction attribute (should be ORed) - fixed scatter list page calculation to point to different pages
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Tomasz Wlostowski authored
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- 24 Aug, 2018 2 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch> Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 23 Aug, 2018 6 commits
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Mixed improvements
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Federico Vaga authored
The bug is that on a second TDC instance, the driver will try to register again the trigger type. The trigger type needs to be registered only once at module_init Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 22 Aug, 2018 5 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Apparently the gn4124 does not handle properly bigger pages. I think I have seen this before in the ADC and indeed thare we do PAGE_SIZE transfers. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 21 Aug, 2018 7 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- 20 Aug, 2018 8 commits
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The driver exports a sysfs attrubte to change the coalescing timeout. A new library funciton can be used to set/get this value; and the test program allows the configuration before an acquisition. Keep in mind that, for FIFOs the configuration is global (users are warned on dmesg) while for DMA it is per-channel. I though it was better to have a common interface for both. Users are warnd in the documentation as well. In the long run, perhaps also the FIFO can have its own register. Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
It is not an IRQ coalescing size, but the size that triggers the dump from the FIFO to the DDR. so, it is internal stuff that does not need to get exposed to the user Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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