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FMC TDC 1ns 5cha - Software
Commit c99af7b0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Federico Vaga
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kernel: hacks to make reset work (still not portable to bitstreams containing… 

kernel: hacks to make reset work (still not portable to bitstreams containing anything else than 2 TDC cores)
parent bfb46984
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Showing with 14 additions and 49 deletions
kernel/ft-spec.c
View file @ c99af7b0
......@@ -22,12 +22,6 @@ static int ft_spec_reset(struct fmctdc_dev *ft)
{
struct spec_dev *spec = (struct spec_dev *)ft->fmc->carrier_data;
dev_info(&ft->fmc->dev, "%s: resetting TDC core through Gennum.\n",
__func__);
/* set local bus clock to 160 MHz. The FPGA can't handle more. */
gennum_writel(spec, 0xE001F04C, 0x808);
/* it takes a while for the PLL to bootstrap.... or not!
We have no possibility to check, as the PLL status register is driven
by the clock from this PLL :( */
......
kernel/ft-svec.c
View file @ c99af7b0
......@@ -33,51 +33,13 @@ static int ft_svec_reset(struct fmctdc_dev *ft)
if (ft->fmc->slot_id != 0)
return 0;
dev_info(&ft->fmc->dev, "Resetting FMCs...\n");
fmc_writel(ft->fmc, TDC_CARRIER_CTL1_RSTN_FMC0 |
TDC_CARRIER_CTL1_RSTN_FMC1,
TDC_SVEC_CARRIER_BASE + TDC_REG_CARRIER_CTL1);
dev_info(&ft->fmc->dev, "Un-resetting FMCs...\n");
tmo = jiffies + 2 * HZ;
while (time_before(jiffies, tmo)) {
uint32_t stat;
stat = fmc_readl(ft->fmc,
TDC_SVEC_CARRIER_BASE + TDC_REG_CARRIER_CTL0);
if ((stat & TDC_CARRIER_CTL0_PLL_STAT_FMC0) &&
(stat & TDC_CARRIER_CTL0_PLL_STAT_FMC1))
return 0;
msleep(10);
}
dev_err(&ft->fmc->dev, "PLL lock timeout.\n");
return -EIO;
}
#if 0
static int ft_svec_copy_timestamps(struct fmctdc_dev *ft, int base_addr,
int size, void *dst)
{
int i;
uint32_t addr;
uint32_t *dptr;
/* no unaligned reads, please. */
if (unlikely(size & 3 || base_addr & 3))
return -EIO;
/* FIXME: use SDB to determine buffer base address
(after fixing the HDL) */
addr = ft->ft_buffer_base + base_addr;
for (i = 0, dptr = (uint32_t *) dst; i < size / 4; i++, dptr++)
*dptr = fmc_readl(ft->fmc, addr + i * 4);
fmc_writel(ft->fmc, 0xff, TDC_SVEC_CARRIER_BASE + TDC_REG_CARRIER_RST);
msleep(3000);
return 0;
}
#endif
struct ft_carrier_specific ft_carrier_svec = {
FT_GATEWARE_SVEC,
......
kernel/hw/tdc_regs.h
View file @ c99af7b0
......@@ -73,9 +73,10 @@
#define TDC_REG_CARRIER_CTL0 0x0 /* a.k.a. Carrier revision/PCB id reg */
#define TDC_REG_CARRIER_STATUS 0x4
#define TDC_REG_CARRIER_CTL1 0x8
#define TDC_REG_CARRIER_RST 0xc
#define TDC_CARRIER_CTL0_PLL_STAT_FMC0 BIT(4)
#define TDC_CARRIER_CTL0_PLL_STAT_FMC1 BIT(5)
#define TDC_CARRIER_CTL0_PLL_STAT_FMC0 BIT(5)
#define TDC_CARRIER_CTL0_PLL_STAT_FMC1 BIT(6)
#define TDC_CARRIER_CTL1_RSTN_FMC0 BIT(3)
#define TDC_CARRIER_CTL1_RSTN_FMC1 BIT(4)
......@@ -98,4 +99,12 @@
#define TDC_SVEC_CARRIER_BASE 0x20000
/* TDC core submodule offsets (wrs to the TDC control registers block) */
#define TDC_MEZZ_I2C_OFFSET (0x2000)
#define TDC_MEZZ_ONEWIRE_OFFSET (-0x1000)
#define TDC_MEZZ_EIC_OFFSET (0x1000)
#define TDC_MEZZ_MEM_OFFSET (0x3000)
#endif /* __TDC_REGISTERS_H */
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