V3-0 - Track width not as defined. Verify layout.
- Verify and correct track width of signals. Verify layout.
Discussion
- JGR: The “Layer Stack Up Detail” table indicates a line width/gap of
0.23/0.30 mm for 50/100 Ω at the top and bottom layers, but finally
the single ended tracks were routed with 0.203 mm (8 mils) width and
~56 Ω
- NV: I don’t think it’s the case for all the lines, but changing the
tracks between TDC chip and FMC connector to 10 mils can be easily
achievable.
- EB: Recommend to change in a future version
- JGR: Some nets of the bus TDC_D[27..0] were routed in the inside
layers with 8 mils of track width. According to my calculations, in
this inside layers the impedance is about 67 Ω > 50 Ω +/- 10%. This
impedance step may degrade the signal quality. I'd prefer to
propose, if you believe it needed, another PCB stack-up to fit
better the 50 ohms impedance requirement without having to change
the routing.
- NV: Please explain… We can also enlarge the tracks on the internal
layers and/or (don’t know if it’s possible) to grow up the internal
layers thickness.
- EB: To check in a future version.
- JGR: Some signals (TDC_IN_FPGA[5..1] and differential pairs by
example) were routed too close. It may cause crosstalk problems. I
would recommend using the 3W separation rule where possible.
- NV: This is the case for many other signals, not only TDC_IN_FPGA.
Not very easy to route those lines elsewhere -> too much vias
around…
- EB: To check in a future version.
- NV: Other things on routing: (if a version 4 is planned)
- On C21, enlarge the tracks on both sides.
- Enlarge the tracks of the TDC_STOP [1-5] to 10-12mils on the
bottom side.
- A few more decoupling capacitors can be placed directly under
the TDC chip (bottom layer). Pins 81, 82 and 86.
- Looking at TDC chip, on the right side of pin 86, there is a via
(x: 4662.5mil, y: 4600mil) there is a small piece of track that
can be removed.
- On VDDC_TDC, a 100nF decoupling capacitor could be added near
pin 1 of TDC chip.
- To check in a future version.