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FMC TDC 1ns 5cha - Gateware
Commit e0addd9d authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use… 

hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface instead
parent 1e074bd0
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hdl/rtl/clks_rsts_manager.vhd
View file @ e0addd9d
......@@ -72,11 +72,11 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific libraries
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -87,50 +87,51 @@ use UNISIM.vcomponents.all;
entity clks_rsts_manager is
generic
(nb_of_reg : integer := 68);
(nb_of_reg : integer := 68;
g_simulation : boolean := false);
port
-- INPUTS
-- INPUTS
-- Clock signal from carrier board
(clk_sys_i : in std_logic; -- 20MHz VCXO on carrier board or 62.5MHz from Xilinx PLL
(clk_sys_i : in std_logic; -- 20MHz VCXO on carrier board or 62.5MHz from Xilinx PLL
-- Clock signals from the TDC mezzanine PLL
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock generated by
acam_refclk_n_i : in std_logic; -- the mezzanine PLL, same as ACAM's input clock
tdc_125m_clk_p_i : in std_logic; -- 125 MHz clock generated by the mezzanine PLL;
tdc_125m_clk_n_i : in std_logic; -- clock of all other TDC core logic
-- Clock signals from the TDC mezzanine PLL
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock generated by
acam_refclk_n_i : in std_logic; -- the mezzanine PLL, same as ACAM's input clock
tdc_125m_clk_p_i : in std_logic; -- 125 MHz clock generated by the mezzanine PLL;
tdc_125m_clk_n_i : in std_logic; -- clock of all other TDC core logic
-- Other signals from the TDC mezzanine PLL
pll_status_i : in std_logic; -- PLL lock detect
pll_sdo_i : in std_logic; -- not used
pll_status_i : in std_logic; -- PLL lock detect
pll_sdo_i : in std_logic; -- not used
-- Reset signal from the GN4124/VME interface
rst_n_i : in std_logic; -- GN4124/VME interface reset
rst_n_i : in std_logic; -- GN4124/VME interface reset
-- Signals from the reg_ctrl unit for the reconfiguration of the DAC
send_dac_word_p_i : in std_logic; -- pulse upon PCIe/VME request for a DAC reconfiguration
dac_word_i : in std_logic_vector(23 downto 0); -- DAC Vout = Vref (dac_word/65536)
send_dac_word_p_i : in std_logic; -- pulse upon PCIe/VME request for a DAC reconfiguration
dac_word_i : in std_logic_vector(23 downto 0); -- DAC Vout = Vref (dac_word/65536)
-- Signals from the White Rabbit unit for the reconfiguration of the DAC
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
-- OUTPUTS
-- OUTPUTS
-- Signals to the rest of the modules of the TDC core
tdc_125m_clk_o : out std_logic; -- 125 MHZ clock
internal_rst_o : out std_logic; -- global reset, synched to tdc_125m_clk_o,
-- /!\ asserted until the 125 MHZ clock from the PLL becomes available
tdc_125m_clk_o : out std_logic; -- 125 MHZ clock
internal_rst_o : out std_logic; -- global reset, synched to tdc_125m_clk_o,
-- /!\ asserted until the 125 MHZ clock from the PLL becomes available
-- Signals to the SPI interface for the PLL and DAC
pll_cs_n_o : out std_logic; -- SPI PLL chip select
pll_dac_sync_n_o : out std_logic; -- SPI DAC chip select
pll_sdi_o : out std_logic; -- SPI data
pll_sclk_o : out std_logic; -- SPI clock
pll_cs_n_o : out std_logic; -- SPI PLL chip select
pll_dac_sync_n_o : out std_logic; -- SPI DAC chip select
pll_sdi_o : out std_logic; -- SPI data
pll_sclk_o : out std_logic; -- SPI clock
-- Signal to the one_hz_gen and acam_timecontrol_interface units
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk rising edge
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk rising edge
-- Signal to the leds_manager unit
pll_status_o : out std_logic); -- PLL lock detect
pll_status_o : out std_logic); -- PLL lock detect
end clks_rsts_manager;
......@@ -141,47 +142,47 @@ end clks_rsts_manager;
architecture rtl of clks_rsts_manager is
-- PLL and DAC configuration state machine
subtype t_wd is std_logic_vector(15 downto 0);
subtype t_byte is std_logic_vector(7 downto 0);
type t_instr is array (nb_of_reg-1 downto 0) of t_wd;
type t_stream is array (nb_of_reg-1 downto 0) of t_byte;
type t_pll_init_st is (config_start, sending_dac_word, sending_pll_instruction, sending_pll_data, rest, done);
signal nxt_config_st : t_pll_init_st;
signal config_st : t_pll_init_st := config_start;
signal config_reg : t_stream;
signal addr : t_instr;
signal pll_word_being_sent : t_wd;
subtype t_wd is std_logic_vector(15 downto 0);
subtype t_byte is std_logic_vector(7 downto 0);
type t_instr is array (nb_of_reg-1 downto 0) of t_wd;
type t_stream is array (nb_of_reg-1 downto 0) of t_byte;
type t_pll_init_st is (config_start, sending_dac_word, sending_pll_instruction, sending_pll_data, rest, done);
signal nxt_config_st : t_pll_init_st;
signal config_st : t_pll_init_st := config_start;
signal config_reg : t_stream;
signal addr : t_instr;
signal pll_word_being_sent : t_wd;
-- Counting of bits and bytes that are being sent
signal pll_bit_being_sent, dac_bit_being_sent : std_logic;
signal bit_being_sent : std_logic;
signal pll_bit_index : integer range 15 downto 0;
signal pll_byte_index : integer range nb_of_reg-1 downto 0;
signal dac_bit_index : integer range 23 downto 0;
signal dac_word : std_logic_vector(23 downto 0);
signal send_dac_word_r_edge_p, dac_only : std_logic;
signal pll_cs_n, dac_cs_n : std_logic;
signal pll_bit_being_sent, dac_bit_being_sent : std_logic;
signal bit_being_sent : std_logic;
signal pll_bit_index : integer range 15 downto 0;
signal pll_byte_index : integer range nb_of_reg-1 downto 0;
signal dac_bit_index : integer range 23 downto 0;
signal dac_word : std_logic_vector(23 downto 0);
signal send_dac_word_r_edge_p, dac_only : std_logic;
signal pll_cs_n, dac_cs_n : std_logic;
-- Synchronizers
signal pll_status_synch, internal_rst_synch : std_logic_vector (1 downto 0);
signal rst_in_synch : std_logic_vector (1 downto 0) := "11";
signal acam_refclk_synch, send_dac_word_p_synch : std_logic_vector (2 downto 0);
signal pll_status_synch, internal_rst_synch : std_logic_vector (1 downto 0);
signal rst_in_synch : std_logic_vector (1 downto 0) := "11";
signal acam_refclk_synch, send_dac_word_p_synch : std_logic_vector (2 downto 0);
-- Clock buffers
signal tdc_clk_buf : std_logic;
signal tdc_clk, acam_refclk : std_logic;
signal tdc_clk_buf : std_logic;
signal tdc_clk, acam_refclk : std_logic;
-- Resets
signal rst : std_logic;
signal rst_cnt : unsigned(7 downto 0) := "00000000";
signal rst : std_logic;
signal rst_cnt : unsigned(7 downto 0) := "00000000";
-- SCLK generation
signal sclk : std_logic;
signal sclk_r_edge, sclk_f_edge, sclk_d1, sclk_d2: std_logic;
signal divider : unsigned(7 downto 0) := "00000000";
signal sclk : std_logic;
signal sclk_r_edge, sclk_f_edge, sclk_d1, sclk_d2 : std_logic;
signal divider : unsigned(4 downto 0) := "00000";
signal sclk_en : std_logic;
-- The PLL circuit AD9516-4 needs to be configured through 68 registers.
-- The values and addresses are obtained through the dedicated Analog Devices software & the datasheet.
constant REG_000 : t_byte := x"18";
constant REG_001 : t_byte := x"00";
constant REG_002 : t_byte := x"10";
constant REG_003 : t_byte := x"C3";
constant REG_004 : t_byte := x"00";
constant REG_000 : t_byte := x"18";
constant REG_001 : t_byte := x"00";
constant REG_002 : t_byte := x"10";
constant REG_003 : t_byte := x"C3";
constant REG_004 : t_byte := x"00";
constant REG_010 : t_byte := x"7C";
constant REG_011 : t_byte := x"01";
......@@ -190,7 +191,7 @@ architecture rtl of clks_rsts_manager is
constant REG_014 : t_byte := x"09";
constant REG_015 : t_byte := x"00";
constant REG_016 : t_byte := x"04";
constant REG_017 : t_byte := x"B4"; -- PLL_STATUS
constant REG_017 : t_byte := x"B4"; -- PLL_STATUS
constant REG_018 : t_byte := x"07";
constant REG_019 : t_byte := x"00";
constant REG_01A : t_byte := x"00";
......@@ -220,7 +221,7 @@ architecture rtl of clks_rsts_manager is
constant REG_0F4 : t_byte := x"0A";
constant REG_0F5 : t_byte := x"0A";
constant REG_140 : t_byte := x"42"; -----REF_CLK
constant REG_140 : t_byte := x"42"; -----REF_CLK
constant REG_141 : t_byte := x"5A";
constant REG_142 : t_byte := x"43";
constant REG_143 : t_byte := x"42";
......@@ -255,8 +256,8 @@ architecture rtl of clks_rsts_manager is
constant REG_231 : t_byte := x"00";
constant REG_232 : t_byte := x"01";
constant SIM_RST : std_logic_vector(31 downto 0):= x"00000400";
constant SYN_RST : std_logic_vector(31 downto 0):= x"00004E20";
constant SIM_RST : std_logic_vector(31 downto 0) := x"00000400";
constant SYN_RST : std_logic_vector(31 downto 0) := x"00004E20";
-- this value may still need adjustment according to the dispersion
-- in the performance of the PLL observed during the production tests
......@@ -273,22 +274,22 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc_clk125_ibuf : IBUFDS
generic map
(DIFF_TERM => true, -- Differential Termination
generic map
(DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map
(O => tdc_clk_buf, -- Buffer output
I => tdc_125m_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => tdc_125m_clk_n_i);-- Diff_n buffer input (connect directly to top-level port)
port map
(O => tdc_clk_buf, -- Buffer output
I => tdc_125m_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => tdc_125m_clk_n_i); -- Diff_n buffer input (connect directly to top-level port)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc_clk125_gbuf : BUFG
port map
port map
(O => tdc_clk,
I => tdc_clk_buf);
-- -- -- -- -- -- -- --
tdc_125m_clk_o <= tdc_clk;
tdc_125m_clk_o <= tdc_clk;
---------------------------------------------------------------------------------------------------
......@@ -303,17 +304,17 @@ begin
-- Synchronous process rst_n_i_synchronizer: Synchronization of the input reset signal rst_n_i,
-- coming from the GN4124/VME interface or a PoR, to the clk_sys_i, using a set of 2 registers.
-- Note that the removal of the reset signal is synchronised.
PoR_synchronizer: process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
rst_in_synch <= rst_in_synch(0) & not rst_n_i;
end if;
end process;
PoR_synchronizer : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
rst_in_synch <= rst_in_synch(0) & not rst_n_i;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Synchronous process pll_status_synchronizer: Synchronization of the pll_status_i input to the
-- clk_sys_i, using a set of 2 registers.
pll_status_synchronizer: process (clk_sys_i)
pll_status_synchronizer : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
......@@ -324,7 +325,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- --
pll_status_o <= pll_status_synch(1);
pll_status_o <= pll_status_synch(1);
---------------------------------------------------------------------------------------------------
......@@ -333,22 +334,22 @@ begin
-- is released. Note that the level of the pll_status signal rather than its rising edge is used,
-- as in the case of a GN4124/VME reset during operation the PLL will remain locked, therefore no
-- rising edge would be detected.
rst_generation: process (clk_sys_i)
rst_generation : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
rst <= '1';
rst <= '1';
else
if pll_status_synch(1) = '1' then
if rst_cnt = "11111111" then
rst <= '0';
rst <= '0';
else
rst <= '1';
rst_cnt <= rst_cnt+1;
end if;
else
rst <= '1';
rst_cnt <= "00000000";
rst <= '1';
rst_cnt <= "00000000";
end if;
end if;
end if;
......@@ -357,14 +358,14 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process internal_rst_synchronizer: Synchronization of the above generated rst signal
-- to the 125MHz tdc_clk, using a set of 2 registers.
Internal_rst_synchronizer: process (tdc_clk)
Internal_rst_synchronizer : process (tdc_clk)
begin
if rising_edge (tdc_clk) then
internal_rst_synch <= internal_rst_synch(0) & rst;
end if;
end process;
-- -- -- -- -- -- -- --
internal_rst_o <= internal_rst_synch(1);
internal_rst_o <= internal_rst_synch(1);
---------------------------------------------------------------------------------------------------
......@@ -373,17 +374,17 @@ begin
---------------------------------------------------------------------------------------------------
acam_refclk31M25_ibuf : IBUFDS
generic map
(DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
generic map
(DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map
port map
(O => acam_refclk,
I => acam_refclk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => acam_refclk_n_i);-- Diff_n buffer input (connect directly to top-level port)
I => acam_refclk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => acam_refclk_n_i); -- Diff_n buffer input (connect directly to top-level port)
---------------------------------------------------------------------------------------------------
acam_refclk_synchronizer: process (tdc_clk)
acam_refclk_synchronizer : process (tdc_clk)
begin
if rising_edge (tdc_clk) then
if internal_rst_synch(1) = '1' then
......@@ -394,7 +395,7 @@ begin
end if;
end process;
-- -- -- -- -- --
acam_refclk_r_edge_p_o <= (not acam_refclk_synch(2)) and acam_refclk_synch(1);
acam_refclk_r_edge_p_o <= (not acam_refclk_synch(2)) and acam_refclk_synch(1);
---------------------------------------------------------------------------------------------------
......@@ -403,7 +404,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Synchronous process send_dac_word_p_synchronizer: Synchronization of the send_dac_word_p_o
-- input to the clk_sys_i, using a set of 3 registers.
send_dac_word_p_synchronizer: process (clk_sys_i)
send_dac_word_p_synchronizer : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
......@@ -414,16 +415,16 @@ begin
end if;
end process;
-- -- -- -- -- -- -- --
send_dac_word_r_edge_p <= (not send_dac_word_p_synch(2)) and send_dac_word_p_synch(1);
send_dac_word_r_edge_p <= (not send_dac_word_p_synch(2)) and send_dac_word_p_synch(1);
---------------------------------------------------------------------------------------------------
-- Synchronous process dac_word_reg: selection of the word to be sent to the DAC.
-- Upon initialization the default word is being sent; otherwise the word received through the VME
-- interface on the DAC_WORD register.
dac_word_reg: process (clk_sys_i)
dac_word_reg : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
if rst_in_synch(1) = '1' then
dac_word <= c_DEFAULT_DAC_WORD;
elsif send_dac_word_r_edge_p = '1' then
dac_word <= dac_word_i;
......@@ -445,13 +446,17 @@ begin
-- after a GN4124/VME command for the reconfiguration of the DAC (send_dac_word_p_i) or
-- after a White Rabbit command for the reconfiguration of the DAC(wrabbit_dac_wr_p_i)
---------------------------------------------------------------------------------------------------
pll_dac_initialization_seq: process (clk_sys_i)
pll_dac_initialization_seq : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' or send_dac_word_r_edge_p = '1' then
config_st <= config_start;
dac_only <= '0';
elsif wrabbit_dac_wr_p_i = '1' then
if rst_in_synch(1) = '1' then
if g_simulation then
config_st <= done;
else
config_st <= config_start;
end if;
dac_only <= '0';
elsif wrabbit_dac_wr_p_i = '1' or send_dac_word_r_edge_p = '1' then
config_st <= config_start;
dac_only <= '1';
else
......@@ -461,111 +466,113 @@ begin
end process;
---------------------------------------------------------------------------------------------------
pll_dac_initialization_comb: process (config_st, dac_bit_index, pll_byte_index, pll_bit_index, sclk,
sclk_r_edge, sclk_f_edge, dac_only)
pll_dac_initialization_comb : process (config_st, dac_bit_index, pll_byte_index, pll_bit_index, sclk,
sclk_r_edge, sclk_f_edge, dac_only)
begin
case config_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when config_start =>
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
-----------------------------------
if sclk_r_edge = '1' then
nxt_config_st <= sending_dac_word;
else
nxt_config_st <= config_start;
end if;
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
sclk_en <= '1';
-----------------------------------
if sclk_r_edge = '1' then
nxt_config_st <= sending_dac_word;
else
nxt_config_st <= config_start;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when sending_dac_word =>
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '0';
-----------------------------------
if dac_bit_index = 0 and sclk_f_edge = '1' and dac_only = '0' then
nxt_config_st <= sending_pll_instruction;
elsif dac_bit_index = 0 and sclk_f_edge = '1' and dac_only = '1' then
nxt_config_st <= done;
else
nxt_config_st <= sending_dac_word;
end if;
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '0';
-----------------------------------
if dac_bit_index = 0 and sclk_f_edge = '1' and dac_only = '0' then
nxt_config_st <= sending_pll_instruction;
elsif dac_bit_index = 0 and sclk_f_edge = '1' and dac_only = '1' then
nxt_config_st <= done;
else
nxt_config_st <= sending_dac_word;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when sending_pll_instruction =>
-----------------------------------
pll_cs_n <= '0';
dac_cs_n <= '1';
-----------------------------------
if pll_bit_index = 0 and sclk_r_edge = '1' then
nxt_config_st <= sending_pll_data;
else
nxt_config_st <= sending_pll_instruction;
end if;
-----------------------------------
pll_cs_n <= '0';
dac_cs_n <= '1';
-----------------------------------
if pll_bit_index = 0 and sclk_r_edge = '1' then
nxt_config_st <= sending_pll_data;
else
nxt_config_st <= sending_pll_instruction;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when sending_pll_data =>
-----------------------------------
pll_cs_n <= '0';
dac_cs_n <= '1';
-----------------------------------
if pll_bit_index = 0 and sclk_r_edge = '1' then
nxt_config_st <= rest;
else
nxt_config_st <= sending_pll_data;
end if;
-----------------------------------
pll_cs_n <= '0';
dac_cs_n <= '1';
-----------------------------------
if pll_bit_index = 0 and sclk_r_edge = '1' then
nxt_config_st <= rest;
else
nxt_config_st <= sending_pll_data;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when rest =>
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
-----------------------------------
if sclk_r_edge = '1' then
if pll_byte_index = 0 then
nxt_config_st <= done;
else
nxt_config_st <= sending_pll_instruction;
end if;
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
-----------------------------------
if sclk_r_edge = '1' then
if pll_byte_index = 0 then
nxt_config_st <= done;
else
nxt_config_st <= rest;
nxt_config_st <= sending_pll_instruction;
end if;
else
nxt_config_st <= rest;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when done =>
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
-----------------------------------
nxt_config_st <= done;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
sclk_en <= '0';
-----------------------------------
nxt_config_st <= done;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
-----------------------------------
nxt_config_st <= config_start;
-----------------------------------
pll_cs_n <= '1';
dac_cs_n <= '1';
-----------------------------------
nxt_config_st <= config_start;
end case;
end process;
end case;
end process;
---------------------------------------------------------------------------------------------------
pll_sclk_generator: process (clk_sys_i) -- transitions take place on the falling edge of sclk
pll_sclk_generator : process (clk_sys_i) -- transitions take place on the falling edge of sclk
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
if rst_in_synch(1) = '1' and sclk_en = '1' then
sclk <= '0';
sclk_d1 <= '0';
sclk_d2 <= '0';
else
sclk_d1 <= sclk;
sclk_d2 <= sclk_d1;
if divider(2) = '1' then
sclk <= '0';
else
sclk <= '1';
if divider = 0 then
sclk <= '0';
elsif divider = 15 then
sclk <= '1';
end if;
end if;
end if;
......@@ -580,7 +587,7 @@ begin
begin
if rising_edge(clk_sys_i) then
if rst_in_synch(1) = '1' then
divider <= (others => '0');
divider <= (others => '0');
else
divider <= divider + 1;
end if;
......@@ -588,31 +595,31 @@ begin
end process;
---------------------------------------------------------------------------------------------------
pll_index_control: process (clk_sys_i) -- counting of bits that are sent on the rising edges
pll_index_control : process (clk_sys_i) -- counting of bits that are sent on the rising edges
begin
if rising_edge (clk_sys_i) then
if rst_in_synch(1) = '1' then
pll_bit_index <= 15;
if rst_in_synch(1) = '1' then
pll_bit_index <= 15;
elsif pll_cs_n = '1' then
pll_bit_index <= 15;
pll_bit_index <= 15;
elsif sclk_r_edge = '1' then
if pll_bit_index = 0 then
pll_bit_index <= 7;
pll_bit_index <= 7;
else
pll_bit_index <= pll_bit_index -1;
pll_bit_index <= pll_bit_index -1;
end if;
end if;
if rst_in_synch(1) = '1' then
pll_byte_index <= nb_of_reg -1;
if rst_in_synch(1) = '1' then
pll_byte_index <= nb_of_reg -1;
elsif config_st = rest and sclk_r_edge = '1' then
if pll_byte_index = 0 then
pll_byte_index <= nb_of_reg-1;
pll_byte_index <= nb_of_reg-1;
else
pll_byte_index <= pll_byte_index -1;
pll_byte_index <= pll_byte_index -1;
end if;
end if;
end if;
......@@ -620,15 +627,15 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
pll_bit_being_sent <= pll_word_being_sent(pll_bit_index);
pll_word_being_sent <= addr(pll_byte_index) when config_st = sending_pll_instruction
pll_word_being_sent <= addr(pll_byte_index) when config_st = sending_pll_instruction
else x"00" & config_reg(pll_byte_index);
---------------------------------------------------------------------------------------------------
dac_index_control: process (clk_sys_i)
dac_index_control : process (clk_sys_i)
begin
if rising_edge (clk_sys_i) then -- counting of bits that are sent on the falling edges
if rising_edge (clk_sys_i) then -- counting of bits that are sent on the falling edges
if rst_in_synch(1) = '1' then
if rst_in_synch(1) = '1' then
dac_bit_index <= 23;
elsif dac_cs_n = '1' and sclk_f_edge = '1' then
......@@ -636,7 +643,7 @@ begin
elsif dac_cs_n = '0' and sclk_f_edge = '1' then
if dac_bit_index = 0 then
dac_bit_index <= 23;
dac_bit_index <= 23;
else
dac_bit_index <= dac_bit_index - 1;
end if;
......@@ -645,8 +652,8 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
dac_bit_being_sent <= dac_word(dac_bit_index);
bit_being_sent <= dac_bit_being_sent when dac_cs_n = '0' else pll_bit_being_sent;
dac_bit_being_sent <= dac_word(dac_bit_index);
bit_being_sent <= dac_bit_being_sent when dac_cs_n = '0' else pll_bit_being_sent;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
pll_sdi_o <= bit_being_sent;
......@@ -823,4 +830,4 @@ begin
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
----------------------------------------------------------------------------------------------------
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ e0addd9d
......@@ -133,10 +133,10 @@ entity fmc_tdc_wrapper is
-- implement direct TDC timestamp readout FIFO, used in the WR Node projects
g_with_direct_readout : boolean := false;
g_use_dma_readout : boolean := false;
g_use_dma_readout : boolean := false;
g_use_fake_timestamps_for_sim : boolean := false
);
);
port
(
clk_sys_i : in std_logic;
......@@ -195,7 +195,7 @@ entity fmc_tdc_wrapper is
mezz_scl_i : in std_logic;
mezz_sda_i : in std_logic;
-- 1-wire interface on TDC mezzanine
mezz_one_wire_b : inout std_logic;
......@@ -222,17 +222,17 @@ entity fmc_tdc_wrapper is
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in := cc_dummy_master_in;
irq_o : out std_logic;
-- local PLL clock output (for WR PTP Core clock disciplining)
clk_125m_tdc_o : out std_logic;
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
sim_timestamp_valid_i : in std_logic := '0';
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
sim_timestamp_valid_i : in std_logic := '0';
sim_timestamp_ready_o : out std_logic
);
);
end fmc_tdc_wrapper;
......@@ -292,11 +292,15 @@ architecture rtl of fmc_tdc_wrapper is
(c_slave_direct => x"00008000",
c_slave_regs => x"00008000");
signal wr_dac_din, wr_dac_sclk, wr_dac_sync_n : std_logic;
signal pll_cs : std_logic;
begin
gen_with_direct_readout : if g_with_direct_readout generate
cmp_mux_host_registers : xwb_crossbar
generic map (
g_num_masters => c_cnx_slave_ports,
......@@ -318,28 +322,29 @@ begin
master_o => cnx_master_out);
cmp_direct_readout : fmc_tdc_direct_readout
port map (
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
direct_timestamp_i => direct_timestamp,
direct_timestamp_wr_i => direct_timestamp_wr,
direct_slave_i => cnx_master_out(c_slave_direct),
direct_slave_o => cnx_master_in(c_slave_direct));
port map (
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
direct_timestamp_i => direct_timestamp,
direct_timestamp_wr_i => direct_timestamp_wr,
direct_slave_i => cnx_master_out(c_slave_direct),
direct_slave_o => cnx_master_in(c_slave_direct));
end generate gen_with_direct_readout;
gen_without_direct_readout: if not g_with_direct_readout generate
gen_without_direct_readout : if not g_with_direct_readout generate
cnx_master_out(c_slave_regs) <= slave_i;
slave_o <= cnx_master_in(c_slave_regs);
slave_o <= cnx_master_in(c_slave_regs);
end generate gen_without_direct_readout;
cmp_tdc_clks_rsts_mgment : clks_rsts_manager
cmp_tdc_clks_rsts_mgment : entity work.clks_rsts_manager
generic map
(nb_of_reg => 68)
(nb_of_reg => 68,
g_simulation => g_simulation)
port map
(clk_sys_i => clk_sys_i,
acam_refclk_p_i => acam_refclk_p_i,
......@@ -349,121 +354,145 @@ begin
rst_n_i => rst_n_a_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
send_dac_word_p_i => send_dac_word_p,
dac_word_i => dac_word,
send_dac_word_p_i => '0',
dac_word_i => x"000000",
acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
wrabbit_dac_value_i => tm_dac_value_i,
wrabbit_dac_wr_p_i => tm_dac_wr_i,
wrabbit_dac_value_i => x"000000",
wrabbit_dac_wr_p_i => '0',
internal_rst_o => rst_125m_mezz,
pll_cs_n_o => pll_cs_o,
pll_cs_n_o => pll_cs,
pll_dac_sync_n_o => pll_dac_sync,
pll_sdi_o => pll_sdi,
pll_sclk_o => pll_sclk,
tdc_125m_clk_o => clk_125m_mezz,
pll_status_o => open);
U_WR_DAC : gc_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => 8,
g_num_cs_select => 1,
g_sclk_polarity => 0)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
value_i => tm_dac_value_i(15 downto 0),
cs_sel_i => "1",
load_i => tm_dac_wr_i,
sclk_divsel_i => "010",
dac_cs_n_o(0) => wr_dac_sync_n,
dac_sclk_o => wr_dac_sclk,
dac_sdata_o => wr_dac_din);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_mezz_n <= not rst_125m_mezz;
pll_dac_sync_o <= pll_dac_sync;
pll_sdi_o <= pll_sdi;
pll_sclk_o <= pll_sclk;
pll_dac_sync_o <= wr_dac_sync_n;
pll_sdi_o <= pll_sdi when pll_cs = '0' else wr_dac_din;
pll_sclk_o <= pll_sclk when pll_cs = '0' else wr_dac_sclk;
pll_cs_o <= pll_cs;
clk_125m_tdc_o <= clk_125m_mezz;
clk_125m_tdc_o <= clk_125m_mezz;
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : entity work.fmc_tdc_mezzanine
generic map
(g_span => 32,
g_width => 32,
g_simulation => g_simulation,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
-- 125M clk and reset
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
-- Wishbone
slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs),
dma_wb_i => dma_wb_i,
dma_wb_o => dma_wb_o,
-- Interrupt line from EIC
wb_irq_o => irq_o,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word,
-- ACAM interface
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
-- Input channels enable
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- WISHBONE interface with the GN4124 core
-- White Rabbit
wrabbit_link_up_i => tm_link_up_i,
wrabbit_time_valid_i => tm_time_valid_i,
wrabbit_cycles_i => tm_cycles_i,
wrabbit_utc_i => tm_tai_i(31 downto 0),
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en_o,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked_i,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i => tm_dac_value_i,
wrabbit_dac_wr_p_i => tm_dac_wr_i,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => mezz_scl_i,
i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => mezz_sda_i,
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
onewire_b => mezz_one_wire_b,
direct_timestamp_o => direct_timestamp,
direct_timestamp_stb_o => direct_timestamp_wr,
sim_timestamp_ready_o => sim_timestamp_ready_o,
sim_timestamp_valid_i => sim_timestamp_valid_i,
sim_timestamp_i => sim_timestamp_i);
mezz_scl_o <= '0' when tdc_scl_out ='0' and tdc_scl_oen = '0' else '1';
mezz_sda_o <= '0' when tdc_sda_out ='0' and tdc_sda_oen = '0' else '1';
end rtl;
cmp_tdc_mezz : entity work.fmc_tdc_mezzanine
generic map
(g_span => 32,
g_width => 32,
g_simulation => g_simulation,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
-- 125M clk and reset
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
-- Wishbone
slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs),
dma_wb_i => dma_wb_i,
dma_wb_o => dma_wb_o,
-- Interrupt line from EIC
wb_irq_o => irq_o,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word,
-- ACAM interface
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
-- Input channels enable
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- WISHBONE interface with the GN4124 core
-- White Rabbit
wrabbit_link_up_i => tm_link_up_i,
wrabbit_time_valid_i => tm_time_valid_i,
wrabbit_cycles_i => tm_cycles_i,
wrabbit_utc_i => tm_tai_i(31 downto 0),
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en_o,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked_i,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i => tm_dac_value_i,
wrabbit_dac_wr_p_i => tm_dac_wr_i,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => mezz_scl_i,
i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => mezz_sda_i,
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
onewire_b => mezz_one_wire_b,
direct_timestamp_o => direct_timestamp,
direct_timestamp_stb_o => direct_timestamp_wr,
sim_timestamp_ready_o => sim_timestamp_ready_o,
sim_timestamp_valid_i => sim_timestamp_valid_i,
sim_timestamp_i => sim_timestamp_i);
mezz_scl_o <= '0' when tdc_scl_out = '0' and tdc_scl_oen = '0' else '1';
mezz_sda_o <= '0' when tdc_sda_out = '0' and tdc_sda_oen = '0' else '1';
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
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