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FMC TDC 1ns 5cha - Gateware
Commit a388eab5 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: make FIFO readout and EIC optional

parent abad9a6f
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Showing with 183 additions and 158 deletions
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ a388eab5
......@@ -111,6 +111,7 @@ entity fmc_tdc_mezzanine is
g_width : integer := 32;
g_simulation : boolean := false;
g_use_dma_readout : boolean := true;
g_use_fifo_readout : boolean := true;
g_use_fake_timestamps_for_sim : boolean := false);
port
-- TDC core
......@@ -326,7 +327,7 @@ begin
g_width => g_width,
g_simulation => g_simulation,
g_with_dma_readout => g_use_dma_readout,
g_with_fifo_readout => true)
g_with_fifo_readout => g_use_fifo_readout)
port map
( -- clks, rst
clk_tdc_i => clk_tdc_i,
......@@ -424,7 +425,7 @@ begin
gen_enable_fifo_readout : if g_use_fifo_readout generate
gen_fifos : for i in 0 to 4 generate
U_TheFifo : entity work.timestamp_fifo
......@@ -448,6 +449,20 @@ begin
timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
end generate gen_fifos;
end generate gen_enable_fifo_readout;
gen_disable_fifo_readout : if not g_use_fifo_readout generate
gen_fifos : for i in 0 to 4 generate
timestamp_ready(i) <= '1';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).ack <= '1';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).stall <= '0';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).err <= '0';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).rty <= '0';
end generate gen_fifos;
end generate gen_disable_fifo_readout;
gen_with_dma_readout : if g_use_dma_readout generate
U_DMA_Engine : entity work.tdc_dma_engine
......@@ -555,6 +570,8 @@ begin
regs_i => regs_ow_in,
regs_o => regs_ow_out);
gen_enable_eic : if g_use_fifo_readout or g_use_dma_readout generate
---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
......@@ -588,6 +605,14 @@ begin
irq_tdc_dma5_i => irq_dma(4)
);
end generate gen_enable_eic;
gen_disable_eic : if not g_use_fifo_readout and not g_use_dma_readout generate
cnx_master_in(c_WB_SLAVE_TDC_EIC).ack <= '1';
cnx_master_in(c_WB_SLAVE_TDC_EIC).stall <= '0';
wb_irq_o <= '0';
end generate gen_disable_eic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TDC_EIC).err <= '0';
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ a388eab5
......@@ -132,10 +132,9 @@ entity fmc_tdc_wrapper is
g_simulation : boolean := false;
-- implement direct TDC timestamp readout FIFO, used in the WR Node projects
g_with_direct_readout : boolean := false;
g_use_dma_readout : boolean := false;
g_use_fifo_readout : boolean := false;
g_use_fake_timestamps_for_sim : boolean := false
);
port
(
......@@ -405,6 +404,7 @@ begin
(g_span => 32,
g_width => 32,
g_simulation => g_simulation,
g_use_fifo_readout => g_use_fifo_readout,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map
......@@ -492,7 +492,7 @@ begin
end rtl;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
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