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FMC TDC 1ns 5cha - Gateware
Commit a388eab5 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: make FIFO readout and EIC optional

parent abad9a6f
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hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ a388eab5
......@@ -111,6 +111,7 @@ entity fmc_tdc_mezzanine is
g_width : integer := 32;
g_simulation : boolean := false;
g_use_dma_readout : boolean := true;
g_use_fifo_readout : boolean := true;
g_use_fake_timestamps_for_sim : boolean := false);
port
-- TDC core
......@@ -177,15 +178,15 @@ entity fmc_tdc_mezzanine is
wb_irq_o : out std_logic;
-- I2C EEPROM interface
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_o : out std_logic;
i2c_sda_i : in std_logic;
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
i2c_scl_i : in std_logic;
i2c_sda_oen_o : out std_logic;
i2c_sda_o : out std_logic;
i2c_sda_i : in std_logic;
-- 1-Wire interface
onewire_b : inout std_logic;
direct_timestamp_o : out std_logic_vector(127 downto 0);
onewire_b : inout std_logic;
direct_timestamp_o : out std_logic_vector(127 downto 0);
direct_timestamp_valid_o : out std_logic;
sim_timestamp_i : in t_tdc_timestamp := c_dummy_timestamp;
......@@ -326,7 +327,7 @@ begin
g_width => g_width,
g_simulation => g_simulation,
g_with_dma_readout => g_use_dma_readout,
g_with_fifo_readout => true)
g_with_fifo_readout => g_use_fifo_readout)
port map
( -- clks, rst
clk_tdc_i => clk_tdc_i,
......@@ -387,7 +388,7 @@ begin
reset_seq_i => reset_seq,
direct_timestamp_valid_o => direct_timestamp_valid_o,
direct_timestamp_o => direct_timestamp_o,
direct_timestamp_o => direct_timestamp_o,
irq_threshold_o => irq_threshold,
irq_timeout_o => irq_timeout,
......@@ -424,30 +425,44 @@ begin
gen_enable_fifo_readout : if g_use_fifo_readout generate
gen_fifos : for i in 0 to 4 generate
gen_fifos : for i in 0 to 4 generate
U_TheFifo : entity work.timestamp_fifo
generic map (
g_channel => i)
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_FIFO0 + i),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i),
irq_o => irq_fifo(i),
enable_i => channel_enable(i),
tick_i => tick_1ms,
irq_threshold_i => irq_threshold,
irq_timeout_i => irq_timeout,
timestamp_i => timestamp,
timestamp_valid_i => timestamp_stb,
ts_offset_o => ts_offset(i),
reset_seq_o => reset_seq(i),
raw_enable_o => raw_enable(i));
timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
end generate gen_fifos;
end generate gen_enable_fifo_readout;
gen_disable_fifo_readout : if not g_use_fifo_readout generate
gen_fifos : for i in 0 to 4 generate
timestamp_ready(i) <= '1';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).ack <= '1';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).stall <= '0';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).err <= '0';
cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i).rty <= '0';
end generate gen_fifos;
end generate gen_disable_fifo_readout;
U_TheFifo : entity work.timestamp_fifo
generic map (
g_channel => i)
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_FIFO0 + i),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i),
irq_o => irq_fifo(i),
enable_i => channel_enable(i),
tick_i => tick_1ms,
irq_threshold_i => irq_threshold,
irq_timeout_i => irq_timeout,
timestamp_i => timestamp,
timestamp_valid_i => timestamp_stb,
ts_offset_o => ts_offset(i),
reset_seq_o => reset_seq(i),
raw_enable_o => raw_enable(i));
timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
end generate gen_fifos;
gen_with_dma_readout : if g_use_dma_readout generate
U_DMA_Engine : entity work.tdc_dma_engine
......@@ -555,6 +570,8 @@ begin
regs_i => regs_ow_in,
regs_o => regs_ow_out);
gen_enable_eic : if g_use_fifo_readout or g_use_dma_readout generate
---------------------------------------------------------------------------------------------------
-- WBGEN2 EMBEDDED INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
......@@ -562,31 +579,39 @@ begin
-- 0 -> number of accumulated timestamps reached threshold
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
cmp_tdc_eic : entity work.tdc_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(5 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o,
irq_tdc_fifo1_i => irq_fifo(0),
irq_tdc_fifo2_i => irq_fifo(1),
irq_tdc_fifo3_i => irq_fifo(2),
irq_tdc_fifo4_i => irq_fifo(3),
irq_tdc_fifo5_i => irq_fifo(4),
irq_tdc_dma1_i => irq_dma(0),
irq_tdc_dma2_i => irq_dma(1),
irq_tdc_dma3_i => irq_dma(2),
irq_tdc_dma4_i => irq_dma(3),
irq_tdc_dma5_i => irq_dma(4)
);
cmp_tdc_eic : entity work.tdc_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(5 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o,
irq_tdc_fifo1_i => irq_fifo(0),
irq_tdc_fifo2_i => irq_fifo(1),
irq_tdc_fifo3_i => irq_fifo(2),
irq_tdc_fifo4_i => irq_fifo(3),
irq_tdc_fifo5_i => irq_fifo(4),
irq_tdc_dma1_i => irq_dma(0),
irq_tdc_dma2_i => irq_dma(1),
irq_tdc_dma3_i => irq_dma(2),
irq_tdc_dma4_i => irq_dma(3),
irq_tdc_dma5_i => irq_dma(4)
);
end generate gen_enable_eic;
gen_disable_eic : if not g_use_fifo_readout and not g_use_dma_readout generate
cnx_master_in(c_WB_SLAVE_TDC_EIC).ack <= '1';
cnx_master_in(c_WB_SLAVE_TDC_EIC).stall <= '0';
wb_irq_o <= '0';
end generate gen_disable_eic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ a388eab5
......@@ -129,13 +129,12 @@ entity fmc_tdc_wrapper is
generic
(
-- reduces some timeouts to speed up simulation
g_simulation : boolean := false;
g_simulation : boolean := false;
-- implement direct TDC timestamp readout FIFO, used in the WR Node projects
g_with_direct_readout : boolean := false;
g_with_direct_readout : boolean := false;
g_use_dma_readout : boolean := false;
g_use_fifo_readout : boolean := false;
g_use_fake_timestamps_for_sim : boolean := false
);
port
(
......@@ -343,7 +342,7 @@ begin
cmp_tdc_clks_rsts_mgment : entity work.clks_rsts_manager
generic map
(nb_of_reg => 68,
(nb_of_reg => 68,
g_simulation => g_simulation)
port map
(clk_sys_i => clk_sys_i,
......@@ -390,109 +389,110 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_125m_mezz_n <= not rst_125m_mezz;
pll_dac_sync_o <= wr_dac_sync_n;
pll_sdi_o <= pll_sdi when pll_cs = '0' else wr_dac_din;
pll_sdi_o <= pll_sdi when pll_cs = '0' else wr_dac_din;
pll_sclk_o <= pll_sclk when pll_cs = '0' else wr_dac_sclk;
pll_cs_o <= pll_cs;
pll_cs_o <= pll_cs;
clk_125m_tdc_o <= clk_125m_mezz;
clk_125m_tdc_o <= clk_125m_mezz;
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : entity work.fmc_tdc_mezzanine
generic map
(g_span => 32,
g_width => 32,
g_simulation => g_simulation,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
-- 125M clk and reset
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
-- Wishbone
slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs),
dma_wb_i => dma_wb_i,
dma_wb_o => dma_wb_o,
-- Interrupt line from EIC
wb_irq_o => irq_o,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word,
-- ACAM interface
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
-- Input channels enable
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- WISHBONE interface with the GN4124 core
-- White Rabbit
wrabbit_link_up_i => tm_link_up_i,
wrabbit_time_valid_i => tm_time_valid_i,
wrabbit_cycles_i => tm_cycles_i,
wrabbit_utc_i => tm_tai_i(31 downto 0),
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en_o,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked_i,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i => tm_dac_value_i,
wrabbit_dac_wr_p_i => tm_dac_wr_i,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => mezz_scl_i,
i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => mezz_sda_i,
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
onewire_b => mezz_one_wire_b,
direct_timestamp_o => direct_timestamp,
direct_timestamp_valid_o => direct_timestamp_wr,
sim_timestamp_ready_o => sim_timestamp_ready_o,
sim_timestamp_valid_i => sim_timestamp_valid_i,
sim_timestamp_i => sim_timestamp_i);
mezz_scl_o <= '0' when tdc_scl_out = '0' and tdc_scl_oen = '0' else '1';
mezz_sda_o <= '0' when tdc_sda_out = '0' and tdc_sda_oen = '0' else '1';
end rtl;
cmp_tdc_mezz : entity work.fmc_tdc_mezzanine
generic map
(g_span => 32,
g_width => 32,
g_simulation => g_simulation,
g_use_fifo_readout => g_use_fifo_readout,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
-- 125M clk and reset
clk_tdc_i => clk_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
-- Wishbone
slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs),
dma_wb_i => dma_wb_i,
dma_wb_o => dma_wb_o,
-- Interrupt line from EIC
wb_irq_o => irq_o,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
send_dac_word_p_o => send_dac_word_p,
dac_word_o => dac_word,
-- ACAM interface
start_from_fpga_o => start_from_fpga_o,
err_flag_i => err_flag_i,
int_flag_i => int_flag_i,
start_dis_o => start_dis_o,
stop_dis_o => stop_dis_o,
data_bus_io => data_bus_io,
address_o => address_o,
cs_n_o => cs_n_o,
oe_n_o => oe_n_o,
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
ef1_i => ef1_i,
ef2_i => ef2_i,
-- Input channels enable
enable_inputs_o => enable_inputs_o,
term_en_1_o => term_en_1_o,
term_en_2_o => term_en_2_o,
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- LEDs on TDC mezzanine
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- WISHBONE interface with the GN4124 core
-- White Rabbit
wrabbit_link_up_i => tm_link_up_i,
wrabbit_time_valid_i => tm_time_valid_i,
wrabbit_cycles_i => tm_cycles_i,
wrabbit_utc_i => tm_tai_i(31 downto 0),
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en_o,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked_i,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
wrabbit_dac_value_i => tm_dac_value_i,
wrabbit_dac_wr_p_i => tm_dac_wr_i,
-- EEPROM I2C on TDC mezzanine
i2c_scl_oen_o => tdc_scl_oen,
i2c_scl_i => mezz_scl_i,
i2c_sda_oen_o => tdc_sda_oen,
i2c_sda_i => mezz_sda_i,
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
onewire_b => mezz_one_wire_b,
direct_timestamp_o => direct_timestamp,
direct_timestamp_valid_o => direct_timestamp_wr,
sim_timestamp_ready_o => sim_timestamp_ready_o,
sim_timestamp_valid_i => sim_timestamp_valid_i,
sim_timestamp_i => sim_timestamp_i);
mezz_scl_o <= '0' when tdc_scl_out = '0' and tdc_scl_oen = '0' else '1';
mezz_sda_o <= '0' when tdc_sda_out = '0' and tdc_sda_oen = '0' else '1';
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
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