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FMC TDC 1ns 5cha - Gateware
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top/svec: single, WR-only top level

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Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Mon Jun 23 18:18:08 2014
par -w -intstyle ise -ol high -xe c -mt off svec_tdc_map.ncd svec_tdc.ncd
svec_tdc.pcf
Constraints file: svec_tdc.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment C:\EDA\Xilinx\v13_4\ISE_DS\ISE\.
"svec_tdc" is an NCD, version 3.2, device xc6slx150t, package fgg900, speed -3
INFO:Par:338 -
Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
speed improvements have shrunk to the point that the time specs are not expected to be met.
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.21 2012-01-07".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 7,035 out of 184,304 3%
Number used as Flip Flops: 6,985
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,194 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 35
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 133
Number with same-slice register load: 58
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,585 out of 23,038 15%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,689
Number with an unused Flip Flop: 4,235 out of 10,689 39%
Number with an unused LUT: 1,495 out of 10,689 13%
Number of fully used LUT-FF pairs: 4,959 out of 10,689 46%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 253 out of 540 46%
Number of LOCed IOBs: 253 out of 253 100%
IOB Flip Flops: 201
Specific Feature Utilization:
Number of RAMB16BWERs: 14 out of 268 5%
Number of RAMB8BWERs: 7 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 138 out of 586 23%
Number used as ILOGIC2s: 138
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 63 out of 586 10%
Number used as OLOGIC2s: 63
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 6 16%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal tdc1_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc2_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 56289 unrouted; REAL time: 21 secs
Phase 2 : 49782 unrouted; REAL time: 27 secs
Phase 3 : 21515 unrouted; REAL time: 1 mins 20 secs
Phase 4 : 21636 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 27 secs
Updating file: svec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:4726, Hold:0, Component Switching Limit:0) REAL time: 6 mins 7 secs
Phase 6 : 0 unrouted; (Setup:104, Hold:0, Component Switching Limit:0) REAL time: 9 mins 18 secs
Updating file: svec_tdc.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:104, Hold:0, Component Switching Limit:0) REAL time: 12 mins 35 secs
Phase 8 : 0 unrouted; (Setup:104, Hold:0, Component Switching Limit:0) REAL time: 12 mins 35 secs
Phase 9 : 0 unrouted; (Setup:104, Hold:0, Component Switching Limit:0) REAL time: 12 mins 35 secs
Phase 10 : 0 unrouted; (Setup:104, Hold:0, Component Switching Limit:0) REAL time: 12 mins 37 secs
Phase 11 : 0 unrouted; (Setup:104, Hold:0, Component Switching Limit:0) REAL time: 12 mins 37 secs
Phase 12 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 12 mins 39 secs
Total REAL time to Router completion: 12 mins 39 secs
Total CPU time to Router completion: 12 mins 10 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| tdc1_125m_clk | BUFGMUX_X3Y7| No | 754 | 0.830 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| tdc2_125m_clk | BUFGMUX_X2Y12| No | 743 | 0.822 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X2Y3| No | 855 | 0.834 | 1.924 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc2/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_76_ | | | | | |
| o_Mux_41_o | Local| | 2 | 0.190 | 0.497 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc1/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_76_ | | | | | |
| o_Mux_41_o | Local| | 2 | 3.582 | 4.144 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 3
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP | SETUP | 0.145ns| 7.855ns| 0| 0
"tdc2_125m_clk_n_i" 8 ns HIGH 50% | HOLD | 0.255ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "td | SETUP | 0.232ns| 7.768ns| 0| 0
c1_125m_clk_p_i" 8 ns HIGH 50% | HOLD | 0.271ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc1_tdc_125m_clk_n_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc1_125m_clk_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_tdc2_tdc_125m_clk_p_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc2_125m_clk_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP | SETUP | 15.799ns| 4.201ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "tdc2_ | HOLD | 0.504ns| | 0| 0
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 17.368ns| 2.632ns| 0| 0
"tdc2_125m_clk" TO TIMEGRP "clk_ | HOLD | 0.393ns| | 0| 0
62m5_sys" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | N/A | N/A| N/A| N/A| N/A
"clk_62m5_sys" TO TIMEGRP "tdc2_ | | | | |
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 12 mins 44 secs
Total CPU time to PAR completion: 12 mins 15 secs
Peak Memory Usage: 563 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 4
Number of info messages: 2
Writing design to file svec_tdc.ncd
PAR done!
hdl/syn/svec/no_wrabbit/svec_tdc.twr deleted 100644 → 0
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hdl/syn/svec/no_wrabbit/svec_tdc.xise deleted 100644 → 0
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hdl/syn/svec/no_wrabbit/svec_tdc_map.map deleted 100644 → 0
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Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'svec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o svec_tdc_map.ncd svec_tdc.ngd svec_tdc.pcf
Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 18:14:34 2014
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 32 secs
Total CPU time at the beginning of Placer: 31 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:8f55c916) REAL time: 39 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:8f55c916) REAL time: 40 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:8f55c916) REAL time: 40 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:a1530eec) REAL time: 54 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:a1530eec) REAL time: 54 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:a1530eec) REAL time: 54 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:a1530eec) REAL time: 55 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:a1530eec) REAL time: 55 secs
Phase 9.8 Global Placement
....................................................
.........................................................................................................................................................................................................
......................................................................................................................................................................................
....................................................................
Phase 9.8 Global Placement (Checksum:da2f71c0) REAL time: 1 mins 56 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:da2f71c0) REAL time: 1 mins 56 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:f94a054e) REAL time: 2 mins 33 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:f94a054e) REAL time: 2 mins 33 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:3b63104b) REAL time: 2 mins 34 secs
Total REAL time to Placer completion: 3 mins 23 secs
Total CPU time to Placer completion: 3 mins 22 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_76_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_76_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 7,035 out of 184,304 3%
Number used as Flip Flops: 6,985
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,194 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 35
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 133
Number with same-slice register load: 58
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,585 out of 23,038 15%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,689
Number with an unused Flip Flop: 4,235 out of 10,689 39%
Number with an unused LUT: 1,495 out of 10,689 13%
Number of fully used LUT-FF pairs: 4,959 out of 10,689 46%
Number of unique control sets: 264
Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 253 out of 540 46%
Number of LOCed IOBs: 253 out of 253 100%
IOB Flip Flops: 201
Specific Feature Utilization:
Number of RAMB16BWERs: 14 out of 268 5%
Number of RAMB8BWERs: 7 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 138 out of 586 23%
Number used as ILOGIC2s: 138
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 63 out of 586 10%
Number used as OLOGIC2s: 63
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 6 16%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 528 MB
Total REAL time to MAP completion: 3 mins 32 secs
Total CPU time to MAP completion: 3 mins 30 secs
Mapping completed.
See MAP report file "svec_tdc_map.mrp" for details.
hdl/syn/svec/no_wrabbit/svec_tdc_map.mrp deleted 100644 → 0
View file @ 3ee4e288
Release 13.4 Map O.87xd (nt)
Xilinx Mapping Report File for Design 'svec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o svec_tdc_map.ncd svec_tdc.ngd svec_tdc.pcf
Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Jun 23 18:14:34 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 3
Slice Logic Utilization:
Number of Slice Registers: 7,035 out of 184,304 3%
Number used as Flip Flops: 6,985
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 46
Number of Slice LUTs: 9,194 out of 92,152 9%
Number used as logic: 9,026 out of 92,152 9%
Number using O6 output only: 5,909
Number using O5 output only: 351
Number using O5 and O6: 2,766
Number used as ROM: 0
Number used as Memory: 35 out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 35
Number using O6 output only: 9
Number using O5 output only: 0
Number using O5 and O6: 26
Number used exclusively as route-thrus: 133
Number with same-slice register load: 58
Number with same-slice carry load: 75
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 3,585 out of 23,038 15%
Nummber of MUXCYs used: 2,428 out of 46,076 5%
Number of LUT Flip Flop pairs used: 10,689
Number with an unused Flip Flop: 4,235 out of 10,689 39%
Number with an unused LUT: 1,495 out of 10,689 13%
Number of fully used LUT-FF pairs: 4,959 out of 10,689 46%
Number of unique control sets: 264
Number of slice register sites lost
to control set restrictions: 486 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 253 out of 540 46%
Number of LOCed IOBs: 253 out of 253 100%
IOB Flip Flops: 201
Specific Feature Utilization:
Number of RAMB16BWERs: 14 out of 268 5%
Number of RAMB8BWERs: 7 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 3 out of 16 18%
Number used as BUFGs: 3
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 138 out of 586 23%
Number used as ILOGIC2s: 138
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 63 out of 586 10%
Number used as OLOGIC2s: 63
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 180 0%
Number of GTPA1_DUALs: 0 out of 4 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 6 16%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.00
Peak Memory Usage: 528 MB
Total REAL time to MAP completion: 3 mins 32 secs
Total CPU time to MAP completion: 3 mins 30 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_76_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_76_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
INFO:LIT:395 - The above info message is repeated 268 more times for the
following (max. 5 shown):
tdc1_in_fpga_1_i,
tdc1_in_fpga_2_i,
tdc1_in_fpga_3_i,
tdc1_in_fpga_4_i,
tdc1_in_fpga_5_i
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) removed
4 block(s) optimized away
256 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block
"cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25" (ROM)
removed.
Loadless block
"cmp_tdc2/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25" (ROM)
removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)"
is sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
GND cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| VME_ADDR_DIR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_ADDR_OE_N_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_ADDR_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_AM_i<0> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<1> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<2> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<3> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<4> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<5> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AS_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_BERR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_DATA_DIR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DATA_OE_N_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DATA_b<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DS_n_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_DS_n_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_DTACK_OE_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DTACK_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_GA_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IACKIN_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IACKOUT_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IACK_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IRQ_n_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_LWORD_n_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_RETRY_OE_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_RETRY_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_RST_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_WRITE_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| carrier_onewire_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| fp_led_column_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| por_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc1_125m_clk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_125m_clk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| tdc1_address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc1_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc1_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_scl_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc1_sda_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc1_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_125m_clk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_125m_clk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| tdc2_address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc2_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc2_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_scl_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc2_sda_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc2_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
hdl/syn/svec/no_wrabbit/wrc.ram deleted 100644 → 0
View file @ 3ee4e288
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/with_wrabbit/wr_svec_tdc.par deleted 100644 → 0
View file @ 3ee4e288
Release 13.4 par O.87xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
PCBE13136:: Tue Jul 08 10:54:36 2014
par -w -intstyle ise -ol high -xe c -mt off wr_svec_tdc_map.ncd wr_svec_tdc.ncd
wr_svec_tdc.pcf
Constraints file: wr_svec_tdc.pcf.
Loading device for application Rf_Device from file '6slx150t.nph' in environment C:\EDA\Xilinx\v13_4\ISE_DS\ISE\.
"wr_svec_tdc" is an NCD, version 3.2, device xc6slx150t, package fgg900, speed -3
INFO:Par:338 -
Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
design even if the time specs can not be met. If you are looking for the best possible design speed available from a
long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
speed improvements have shrunk to the point that the time specs are not expected to be met.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.21 2012-01-07".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 11,682 out of 184,304 6%
Number used as Flip Flops: 11,631
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,122 out of 92,152 17%
Number used as logic: 15,780 out of 92,152 17%
Number using O6 output only: 11,157
Number using O5 output only: 844
Number using O5 and O6: 3,779
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 63
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 255
Number with same-slice register load: 150
Number with same-slice carry load: 105
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,416 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,651
Number with an unused Flip Flop: 7,970 out of 18,651 42%
Number with an unused LUT: 2,529 out of 18,651 13%
Number of fully used LUT-FF pairs: 8,152 out of 18,651 43%
Number of slice register sites lost
to control set restrictions: 0 out of 184,304 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 269 out of 540 49%
Number of LOCed IOBs: 269 out of 269 100%
IOB Flip Flops: 203
Number of bonded IPADs: 4 out of 32 12%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 16 12%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
Number of RAMB8BWERs: 13 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 6 out of 16 37%
Number used as BUFGs: 6
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 139 out of 586 23%
Number used as ILOGIC2s: 139
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 64 out of 586 10%
Number used as OLOGIC2s: 64
Number used as OSERDES2s: 0
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 180 1%
Number of GTPA1_DUALs: 1 out of 4 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 2 out of 6 33%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 30 secs
Finished initial Timing Analysis. REAL time: 30 secs
WARNING:Par:288 - The signal sfp_tx_fault_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal sfp_los_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc1_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal tdc2_pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
PAR will not attempt to route this signal.
Starting Router
Phase 1 : 102859 unrouted; REAL time: 34 secs
Phase 2 : 91138 unrouted; REAL time: 45 secs
Phase 3 : 42992 unrouted; REAL time: 2 mins 50 secs
Phase 4 : 42992 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 56 secs
Updating file: wr_svec_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins
Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 4 mins 2 secs
Total REAL time to Router completion: 4 mins 3 secs
Total CPU time to Router completion: 3 mins 50 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_62m5_sys | BUFGMUX_X2Y3| No | 2267 | 0.839 | 1.923 |
+---------------------+--------------+------+------+------------+-------------+
| clk_dmtd | BUFGMUX_X3Y13| No | 117 | 0.147 | 1.411 |
+---------------------+--------------+------+------+------------+-------------+
|clk_125m_pllref_BUFG | | | | | |
| | BUFGMUX_X2Y4| No | 142 | 0.314 | 1.411 |
+---------------------+--------------+------+------+------------+-------------+
| tdc1_125m_clk | BUFGMUX_X3Y7| No | 748 | 0.832 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| tdc2_125m_clk | BUFGMUX_X2Y12| No | 738 | 0.830 | 1.916 |
+---------------------+--------------+------+------+------------+-------------+
| phy_rx_rbclk | BUFGMUX_X3Y8| No | 140 | 0.193 | 1.427 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F2 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|U_Buf_CLK_GTP_ML_IBU | | | | | |
| F1 | Local| | 1 | 0.000 | 0.002 |
+---------------------+--------------+------+------+------------+-------------+
|U_WR_CORE/WRPC/LM32_ | | | | | |
|CORE/gen_profile_med | | | | | |
|ium_icache_debug.U_W | | | | | |
| rapped_LM32/jtck | Local| | 9 | 0.244 | 7.114 |
+---------------------+--------------+------+------+------------+-------------+
| clk_125m_gtp | Local| | 1 | 0.000 | 0.001 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc2/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_290 | | | | | |
| _o_Mux_41_o | Local| | 2 | 1.187 | 2.006 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_tdc1/cmp_tdc_cor | | | | | |
|e/data_engine_block/ | | | | | |
|engine_st[3]_PWR_290 | | | | | |
| _o_Mux_41_o | Local| | 2 | 0.000 | 0.302 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 6
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_tdc1_125m_clk_p_i = PERIOD TIMEGRP "td | SETUP | 0.255ns| 7.745ns| 0| 0
c1_125m_clk_p_i" 8 ns HIGH 50% | HOLD | 0.346ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc2_tdc_125m_clk_n_i = PERIOD TIMEGRP | SETUP | 0.293ns| 7.707ns| 0| 0
"tdc2_125m_clk_n_i" 8 ns HIGH 50% | HOLD | 0.247ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | SETUP | 0.977ns| 7.023ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | HOLD | 0.311ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | MINPERIOD | 1.750ns| 6.250ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_gtp_n_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
_125m_gtp_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_tdc1_tdc_125m_clk_n_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc1_125m_clk_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_tdc2_tdc_125m_clk_p_i = PERIOD TIMEGRP | MINPERIOD | 4.876ns| 3.124ns| 0| 0
"tdc2_125m_clk_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock3 = MAXDELAY FROM TIMEGRP | SETUP | 10.800ns| 9.200ns| 0| 0
"clk_62m5_sys" TO TIMEGRP "tdc2_ | HOLD | 0.557ns| | 0| 0
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 16.122ns| 3.878ns| 0| 0
"tdc2_125m_clk" TO TIMEGRP "clk_ | HOLD | 0.473ns| | 0| 0
62m5_sys" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | N/A | N/A| N/A| N/A| N/A
"clk_62m5_sys" TO TIMEGRP "tdc2_ | | | | |
125m_clk" 20 ns DATAPATHONLY | | | | |
----------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 4 mins 12 secs
Total CPU time to PAR completion: 3 mins 58 secs
Peak Memory Usage: 655 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 12
Number of info messages: 2
Writing design to file wr_svec_tdc.ncd
PAR done!
hdl/syn/svec/with_wrabbit/wr_svec_tdc.twr deleted 100644 → 0
View file @ 3ee4e288
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.map deleted 100644 → 0
View file @ 3ee4e288
Release 13.4 Map O.87xd (nt)
Xilinx Map Application Log File for Design 'wr_svec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o wr_svec_tdc_map.ncd wr_svec_tdc.ngd
wr_svec_tdc.pcf
Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 08 10:48:00 2014
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 54 secs
Total CPU time at the beginning of Placer: 50 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:b36b8248) REAL time: 1 mins 5 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:b36b8248) REAL time: 1 mins 7 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:131da998) REAL time: 1 mins 7 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:947c35ac) REAL time: 1 mins 26 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:947c35ac) REAL time: 1 mins 26 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:947c35ac) REAL time: 1 mins 26 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:947c35ac) REAL time: 1 mins 27 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:947c35ac) REAL time: 1 mins 27 secs
Phase 9.8 Global Placement
.....................
................................................................................
.........................................................................................................................................................
.........................................................................................................................................
.....................................................................................................................................
Phase 9.8 Global Placement (Checksum:acc0a8e6) REAL time: 3 mins 42 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:acc0a8e6) REAL time: 3 mins 43 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:2df3d620) REAL time: 4 mins 33 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:2df3d620) REAL time: 4 mins 34 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:fa538ed7) REAL time: 4 mins 35 secs
Total REAL time to Placer completion: 6 mins 16 secs
Total CPU time to Placer completion: 6 mins 3 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
.U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
READ_FIRST mode has certain restrictions. Make sure that there is no address
collision. A read/write on one port and a write operation from the other port
at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
bits wide, A13-7 including A5 cannot be the same. Violating this restriction
may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 10
Slice Logic Utilization:
Number of Slice Registers: 11,682 out of 184,304 6%
Number used as Flip Flops: 11,631
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,122 out of 92,152 17%
Number used as logic: 15,780 out of 92,152 17%
Number using O6 output only: 11,157
Number using O5 output only: 844
Number using O5 and O6: 3,779
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 63
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 255
Number with same-slice register load: 150
Number with same-slice carry load: 105
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,416 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,651
Number with an unused Flip Flop: 7,970 out of 18,651 42%
Number with an unused LUT: 2,529 out of 18,651 13%
Number of fully used LUT-FF pairs: 8,152 out of 18,651 43%
Number of unique control sets: 502
Number of slice register sites lost
to control set restrictions: 1,224 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 269 out of 540 49%
Number of LOCed IOBs: 269 out of 269 100%
IOB Flip Flops: 203
Number of bonded IPADs: 4 out of 32 12%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 16 12%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
Number of RAMB8BWERs: 13 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 6 out of 16 37%
Number used as BUFGs: 6
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 139 out of 586 23%
Number used as ILOGIC2s: 139
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 64 out of 586 10%
Number used as OLOGIC2s: 64
Number used as OSERDES2s: 0
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 180 1%
Number of GTPA1_DUALs: 1 out of 4 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 2 out of 6 33%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 6 mins 34 secs
Total CPU time to MAP completion: 6 mins 19 secs
Mapping completed.
See MAP report file "wr_svec_tdc_map.mrp" for details.
hdl/syn/svec/with_wrabbit/wr_svec_tdc_map.mrp deleted 100644 → 0
View file @ 3ee4e288
Release 13.4 Map O.87xd (nt)
Xilinx Mapping Report File for Design 'wr_svec_tdc'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx150t-fgg900-3 -w -logic_opt off -ol
high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
off -pr b -lc off -power off -o wr_svec_tdc_map.ncd wr_svec_tdc.ngd
wr_svec_tdc.pcf
Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Jul 08 10:48:00 2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 10
Slice Logic Utilization:
Number of Slice Registers: 11,682 out of 184,304 6%
Number used as Flip Flops: 11,631
Number used as Latches: 4
Number used as Latch-thrus: 0
Number used as AND/OR logics: 47
Number of Slice LUTs: 16,122 out of 92,152 17%
Number used as logic: 15,780 out of 92,152 17%
Number using O6 output only: 11,157
Number using O5 output only: 844
Number using O5 and O6: 3,779
Number used as ROM: 0
Number used as Memory: 87 out of 21,680 1%
Number used as Dual Port RAM: 24
Number using O6 output only: 24
Number using O5 output only: 0
Number using O5 and O6: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 63
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 38
Number used exclusively as route-thrus: 255
Number with same-slice register load: 150
Number with same-slice carry load: 105
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 6,416 out of 23,038 27%
Nummber of MUXCYs used: 3,592 out of 46,076 7%
Number of LUT Flip Flop pairs used: 18,651
Number with an unused Flip Flop: 7,970 out of 18,651 42%
Number with an unused LUT: 2,529 out of 18,651 13%
Number of fully used LUT-FF pairs: 8,152 out of 18,651 43%
Number of unique control sets: 502
Number of slice register sites lost
to control set restrictions: 1,224 out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 269 out of 540 49%
Number of LOCed IOBs: 269 out of 269 100%
IOB Flip Flops: 203
Number of bonded IPADs: 4 out of 32 12%
Number of LOCed IPADs: 4 out of 4 100%
Number of bonded OPADs: 2 out of 16 12%
Number of LOCed OPADs: 2 out of 2 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
Number of RAMB8BWERs: 13 out of 536 2%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 6 out of 16 37%
Number used as BUFGs: 6
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 12 0%
Number of ILOGIC2/ISERDES2s: 139 out of 586 23%
Number used as ILOGIC2s: 139
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 586 0%
Number of OLOGIC2/OSERDES2s: 64 out of 586 10%
Number used as OLOGIC2s: 64
Number used as OSERDES2s: 0
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 180 1%
Number of GTPA1_DUALs: 1 out of 4 25%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCIE_A1s: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 2 out of 6 33%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 608 MB
Total REAL time to MAP completion: 6 mins 34 secs
Total CPU time to MAP completion: 6 mins 19 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc2/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
cmp_tdc1/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_290_o_Mux_41_o is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
not drive any load pins in the design.
WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
.U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
READ_FIRST mode has certain restrictions. Make sure that there is no address
collision. A read/write on one port and a write operation from the other port
at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
bits wide, A13-7 including A5 cannot be the same. Violating this restriction
may result in the incorrect operation of the BRAM.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network VME_BBSY_n_i has no load.
INFO:LIT:395 - The above info message is repeated 271 more times for the
following (max. 5 shown):
tdc1_in_fpga_1_i,
tdc1_in_fpga_2_i,
tdc1_in_fpga_3_i,
tdc1_in_fpga_4_i,
tdc1_in_fpga_5_i
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) removed
4 block(s) optimized away
256 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block
"cmp_tdc1/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25" (ROM)
removed.
Loadless block
"cmp_tdc2/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25" (ROM)
removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)"
is sourceless and has been removed.
The signal "cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)"
is sourceless and has been removed.
The signal "cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)"
is sourceless and has been removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_tdc1/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
GND cmp_tdc2/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| VME_ADDR_DIR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_ADDR_OE_N_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_ADDR_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_ADDR_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_AM_i<0> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<1> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<2> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<3> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<4> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AM_i<5> | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| VME_AS_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_BERR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_DATA_DIR_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DATA_OE_N_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DATA_b<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<16> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<17> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<18> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<19> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<20> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<21> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<22> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<23> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<24> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<25> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<26> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<27> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<28> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<29> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<30> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DATA_b<31> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| VME_DS_n_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_DS_n_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_DTACK_OE_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_DTACK_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_GA_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<4> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_GA_i<5> | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IACKIN_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IACKOUT_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IACK_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_IRQ_n_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_IRQ_n_o<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| VME_LWORD_n_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | IFF | | |
| | | | | | | | OFF | | |
| VME_RETRY_OE_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_RETRY_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
| VME_RST_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| VME_WRITE_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| carrier_onewire_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| clk_125m_gtp_n_i | IPAD | INPUT | | | | | | | |
| clk_125m_gtp_p_i | IPAD | INPUT | | | | | | | |
| clk_125m_pllref_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_125m_pllref_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| clk_20m_vcxo_i | IOB | INPUT | LVCMOS33 | | | | | | |
| fp_led_column_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_column_o<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| fp_led_line_oen_o<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pcb_ver_i<0> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<1> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<2> | IOB | INPUT | LVCMOS33 | | | | | | |
| pcb_ver_i<3> | IOB | INPUT | LVCMOS33 | | | | | | |
| pll20dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| por_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_los_i | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_mod_def0_b | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_mod_def1_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| sfp_mod_def2_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| sfp_rxn_i | IPAD | INPUT | | | | | | | |
| sfp_rxp_i | IPAD | INPUT | | | | | | | |
| sfp_tx_disable_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| sfp_tx_fault_i | IOB | INPUT | LVCMOS33 | | | | | | |
| sfp_txn_o | OPAD | OUTPUT | | | | | | | |
| sfp_txp_o | OPAD | OUTPUT | | | | | | | |
| tdc1_125m_clk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_125m_clk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc1_acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| tdc1_address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc1_ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc1_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc1_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc1_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_scl_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| tdc1_sda_b | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| tdc1_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc1_term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc1_wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_125m_clk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_125m_clk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
| tdc2_acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
| tdc2_address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
| tdc2_ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_dac_sync_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
| tdc2_pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
| tdc2_prsntm2c_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| tdc2_rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_scl_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc2_sda_b | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| tdc2_start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| tdc2_term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| tdc2_wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
| uart_rxd_i | IOB | INPUT | LVCMOS33 | | | | IFF | | |
| uart_txd_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | OFF | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.
hdl/syn/svec/with_wrabbit/wrc.ram deleted 100644 → 0
View file @ 3ee4e288
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/top/svec/Manifest.py
View file @ 92b7f5e7
......@@ -2,13 +2,13 @@ files = ["synthesis_descriptor.vhd",
"wr_svec_tdc.ucf",
"wr_svec_tdc.vhd"];
fetchto = "../../../ip_cores"
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../../rtl/",
"../../../ip_cores/vme64x-core",
"../../../ip_cores/general-cores",
"../../../ip_cores/wr-cores"
"local" : [ "../../rtl/",
"../../ip_cores/vme64x-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"
]
}
hdl/top/svec/wr_svec_tdc.ucf
View file @ 92b7f5e7
......@@ -4,8 +4,8 @@
NET "tdc1_prsntm2c_n_i" LOC = N30;
NET "tdc2_prsntm2c_n_i" LOC = AE29;
NET "tdc1_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "tdc2_prsntm2c_n_i" IOSTANDARD = "LVCMOS33";
NET "tdc1_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
NET "tdc2_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
#----------------------------------------
# FMC1/FMC2 I2C
......@@ -16,18 +16,17 @@ NET "tdc1_sda_b" LOC = P30;
NET "tdc2_scl_b" LOC = W29;
NET "tdc2_sda_b" LOC = V30;
NET "tdc1_scl_b" IOSTANDARD = "LVCMOS33";
NET "tdc1_sda_b" IOSTANDARD = "LVCMOS33";
NET "tdc1_scl_b" IOSTANDARD = LVCMOS33;
NET "tdc1_sda_b" IOSTANDARD = LVCMOS33;
NET "tdc2_scl_b" IOSTANDARD = "LVCMOS33";
NET "tdc2_sda_b" IOSTANDARD = "LVCMOS33";
NET "tdc2_scl_b" IOSTANDARD = LVCMOS33;
NET "tdc2_sda_b" IOSTANDARD = LVCMOS33;
#----------------------------------------
# Carrier 1-Wire
#----------------------------------------
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS33";
NET "carrier_onewire_b" IOSTANDARD = LVCMOS33;
#----------------------------------------
# PCB version
......@@ -37,10 +36,10 @@ NET "pcb_ver_i[1]" LOC = AE20;
NET "pcb_ver_i[2]" LOC = AD18;
NET "pcb_ver_i[3]" LOC = AE17;
NET "pcb_ver_i[0]" IOSTANDARD="LVCMOS33";
NET "pcb_ver_i[1]" IOSTANDARD="LVCMOS33";
NET "pcb_ver_i[2]" IOSTANDARD="LVCMOS33";
NET "pcb_ver_i[3]" IOSTANDARD="LVCMOS33";
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS33;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS33;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS33;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS33;
#----------------------------------------
# SVEC front panel LEDs
......@@ -54,221 +53,221 @@ NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[0]" IOSTANDARD = LVCMOS33;
NET "fp_led_line_oen_o[1]" IOSTANDARD = LVCMOS33;
NET "fp_led_line_o[0]" IOSTANDARD = LVCMOS33;
NET "fp_led_line_o[1]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[0]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[1]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[2]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[3]" IOSTANDARD = LVCMOS33;
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
NET "VME_WRITE_n_i" LOC = R1;
NET "VME_RST_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y7;
NET "vme_ds_n_i[0]" LOC = Y6;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[6]" LOC = R7;
NET "vme_irq_n_o[5]" LOC = AH2;
NET "vme_irq_n_o[4]" LOC = AF2;
NET "vme_irq_n_o[3]" LOC = N9;
NET "vme_irq_n_o[2]" LOC = N10;
NET "vme_irq_n_o[1]" LOC = AH4;
NET "vme_irq_n_o[0]" LOC = AG4;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD = "LVCMOS33";
NET "VME_RETRY_OE_o" LOC = R4;
NET "VME_RETRY_n_o" LOC = AB2;
NET "VME_LWORD_n_b" LOC = M7;
NET "VME_IACKOUT_n_o" LOC = N3;
NET "VME_IACKIN_n_i" LOC = P7;
NET "VME_IACK_n_i" LOC = N1;
NET "VME_GA_i[5]" LOC = M6;
NET "VME_DTACK_OE_o" LOC = T1;
NET "VME_DTACK_n_o" LOC = R5;
NET "VME_DS_n_i[1]" LOC = Y7;
NET "VME_DS_n_i[0]" LOC = Y6;
NET "VME_DATA_OE_N_o" LOC = P1;
NET "VME_DATA_DIR_o" LOC = P2;
NET "VME_BERR_o" LOC = R3;
NET "VME_AS_n_i" LOC = P6;
NET "VME_ADDR_OE_N_o" LOC = N4;
NET "VME_ADDR_DIR_o" LOC = N5;
NET "VME_IRQ_n_o[6]" LOC = R7;
NET "VME_IRQ_n_o[5]" LOC = AH2;
NET "VME_IRQ_n_o[4]" LOC = AF2;
NET "VME_IRQ_n_o[3]" LOC = N9;
NET "VME_IRQ_n_o[2]" LOC = N10;
NET "VME_IRQ_n_o[1]" LOC = AH4;
NET "VME_IRQ_n_o[0]" LOC = AG4;
NET "VME_GA_i[4]" LOC = V9;
NET "VME_GA_i[3]" LOC = V10;
NET "VME_GA_i[2]" LOC = AJ1;
NET "VME_GA_i[1]" LOC = AH1;
NET "VME_GA_i[0]" LOC = V7;
NET "VME_DATA_b[31]" LOC = AK3;
NET "VME_DATA_b[30]" LOC = AH3;
NET "VME_DATA_b[29]" LOC = T8;
NET "VME_DATA_b[28]" LOC = T9;
NET "VME_DATA_b[27]" LOC = AK4;
NET "VME_DATA_b[26]" LOC = AJ4;
NET "VME_DATA_b[25]" LOC = W6;
NET "VME_DATA_b[24]" LOC = W7;
NET "VME_DATA_b[23]" LOC = AB6;
NET "VME_DATA_b[22]" LOC = AB7;
NET "VME_DATA_b[21]" LOC = W9;
NET "VME_DATA_b[20]" LOC = W10;
NET "VME_DATA_b[19]" LOC = AK5;
NET "VME_DATA_b[18]" LOC = AH5;
NET "VME_DATA_b[17]" LOC = AD6;
NET "VME_DATA_b[16]" LOC = AC6;
NET "VME_DATA_b[15]" LOC = AA6;
NET "VME_DATA_b[14]" LOC = AA7;
NET "VME_DATA_b[13]" LOC = T6;
NET "VME_DATA_b[12]" LOC = T7;
NET "VME_DATA_b[11]" LOC = AG5;
NET "VME_DATA_b[10]" LOC = AE5;
NET "VME_DATA_b[9]" LOC = Y11;
NET "VME_DATA_b[8]" LOC = W11;
NET "VME_DATA_b[7]" LOC = AF6;
NET "VME_DATA_b[6]" LOC = AE6;
NET "VME_DATA_b[5]" LOC = Y8;
NET "VME_DATA_b[4]" LOC = Y9;
NET "VME_DATA_b[3]" LOC = AE7;
NET "VME_DATA_b[2]" LOC = AD7;
NET "VME_DATA_b[1]" LOC = AA9;
NET "VME_DATA_b[0]" LOC = AA10;
NET "VME_AM_i[5]" LOC = V8;
NET "VME_AM_i[4]" LOC = AG3;
NET "VME_AM_i[3]" LOC = AF3;
NET "VME_AM_i[2]" LOC = AF4;
NET "VME_AM_i[1]" LOC = AE4;
NET "VME_AM_i[0]" LOC = AK2;
NET "VME_ADDR_b[31]" LOC = T2;
NET "VME_ADDR_b[30]" LOC = T3;
NET "VME_ADDR_b[29]" LOC = T4;
NET "VME_ADDR_b[28]" LOC = U1;
NET "VME_ADDR_b[27]" LOC = U3;
NET "VME_ADDR_b[26]" LOC = U4;
NET "VME_ADDR_b[25]" LOC = U5;
NET "VME_ADDR_b[24]" LOC = V1;
NET "VME_ADDR_b[23]" LOC = V2;
NET "VME_ADDR_b[22]" LOC = W1;
NET "VME_ADDR_b[21]" LOC = W3;
NET "VME_ADDR_b[20]" LOC = AA4;
NET "VME_ADDR_b[19]" LOC = AA5;
NET "VME_ADDR_b[18]" LOC = Y1;
NET "VME_ADDR_b[17]" LOC = Y2;
NET "VME_ADDR_b[16]" LOC = Y3;
NET "VME_ADDR_b[15]" LOC = Y4;
NET "VME_ADDR_b[14]" LOC = AC1;
NET "VME_ADDR_b[13]" LOC = AC3;
NET "VME_ADDR_b[12]" LOC = AD1;
NET "VME_ADDR_b[11]" LOC = AD2;
NET "VME_ADDR_b[10]" LOC = AB3;
NET "VME_ADDR_b[9]" LOC = AB4;
NET "VME_ADDR_b[8]" LOC = AD3;
NET "VME_ADDR_b[7]" LOC = AD4;
NET "VME_ADDR_b[6]" LOC = AC4;
NET "VME_ADDR_b[5]" LOC = AC5;
NET "VME_ADDR_b[4]" LOC = N7;
NET "VME_ADDR_b[3]" LOC = N8;
NET "VME_ADDR_b[2]" LOC = AE1;
NET "VME_ADDR_b[1]" LOC = AE3;
NET "VME_WRITE_n_i" IOSTANDARD = LVCMOS33;
NET "VME_RST_n_i" IOSTANDARD = LVCMOS33;
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[0]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
NET "VME_RETRY_OE_o" IOSTANDARD = LVCMOS33;
NET "VME_RETRY_n_o" IOSTANDARD = LVCMOS33;
NET "VME_LWORD_n_b" IOSTANDARD = LVCMOS33;
NET "VME_IACKOUT_n_o" IOSTANDARD = LVCMOS33;
NET "VME_IACKIN_n_i" IOSTANDARD = LVCMOS33;
NET "VME_IACK_n_i" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[5]" IOSTANDARD = LVCMOS33;
NET "VME_DTACK_OE_o" IOSTANDARD = LVCMOS33;
NET "VME_DTACK_n_o" IOSTANDARD = LVCMOS33;
NET "VME_DS_n_i[1]" IOSTANDARD = LVCMOS33;
NET "VME_DS_n_i[0]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_OE_N_o" IOSTANDARD = LVCMOS33;
NET "VME_DATA_DIR_o" IOSTANDARD = LVCMOS33;
NET "VME_BERR_o" IOSTANDARD = LVCMOS33;
NET "VME_AS_n_i" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_OE_N_o" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_DIR_o" IOSTANDARD = LVCMOS33;
NET "VME_IRQ_n_o[6]" IOSTANDARD = LVCMOS33;
NET "VME_IRQ_n_o[5]" IOSTANDARD = LVCMOS33;
NET "VME_IRQ_n_o[4]" IOSTANDARD = LVCMOS33;
NET "VME_IRQ_n_o[3]" IOSTANDARD = LVCMOS33;
NET "VME_IRQ_n_o[2]" IOSTANDARD = LVCMOS33;
NET "VME_IRQ_n_o[1]" IOSTANDARD = LVCMOS33;
NET "VME_IRQ_n_o[0]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[4]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[3]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[2]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[1]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[0]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[31]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[30]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[29]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[28]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[27]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[26]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[25]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[24]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[23]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[22]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[21]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[20]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[19]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[18]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[17]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[16]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[15]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[14]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[13]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[12]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[11]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[10]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[9]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[8]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[7]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[6]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[5]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[4]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[3]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[2]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[1]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[0]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[5]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[4]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[3]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[2]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[1]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[0]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[31]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[30]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[29]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[28]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[27]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[26]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[25]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[24]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[23]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[22]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[21]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[20]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[19]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[18]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[17]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[16]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[15]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[14]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[13]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[12]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[11]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[10]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[9]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[8]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[7]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[6]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[5]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[4]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[3]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[2]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[1]" IOSTANDARD = LVCMOS33;
#----------------------------------------
......@@ -277,285 +276,285 @@ NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "tdc1_acam_refclk_p_i" LOC = "H15";
NET "tdc1_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "tdc1_acam_refclk_n_i" LOC = "G15";
NET "tdc1_acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "tdc1_125m_clk_p_i" LOC = "E16";
NET "tdc1_125m_clk_p_i" IOSTANDARD = "LVDS_25";
NET "tdc1_125m_clk_n_i" LOC = "D16";
NET "tdc1_125m_clk_n_i" IOSTANDARD = "LVDS_25";
NET "tdc1_led_trig1_o" LOC = "H13";
NET "tdc1_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_led_trig2_o" LOC = "H11";
NET "tdc1_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_led_trig3_o" LOC = "G11";
NET "tdc1_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_term_en_1_o" LOC = "C16";
NET "tdc1_term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_term_en_2_o" LOC = "A16";
NET "tdc1_term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_ef1_i" LOC = "F19";
NET "tdc1_ef1_i" IOSTANDARD = "LVCMOS25";
NET "tdc1_ef2_i" LOC = "E19";
NET "tdc1_ef2_i" IOSTANDARD = "LVCMOS25";
NET "tdc1_term_en_3_o" LOC = "F15";
NET "tdc1_term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_term_en_4_o" LOC = "E15";
NET "tdc1_term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_term_en_5_o" LOC = "F13";
NET "tdc1_term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_led_status_o" LOC = "E13";
NET "tdc1_led_status_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_led_trig4_o" LOC = "L11";
NET "tdc1_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_led_trig5_o" LOC = "K11";
NET "tdc1_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_pll_sclk_o" LOC = "M15";
NET "tdc1_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_pll_dac_sync_n_o" LOC = "K15";
NET "tdc1_pll_dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_pll_cs_n_o" LOC = "L14";
NET "tdc1_pll_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_cs_n_o" LOC = "K14";
NET "tdc1_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_err_flag_i" LOC = "H16";
NET "tdc1_err_flag_i" IOSTANDARD = "LVCMOS25";
NET "tdc1_int_flag_i" LOC = "G16";
NET "tdc1_int_flag_i" IOSTANDARD = "LVCMOS25";
NET "tdc1_start_dis_o" LOC = "F11";
NET "tdc1_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_stop_dis_o" LOC = "E11";
NET "tdc1_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_pll_sdo_i" LOC = "L13";
NET "tdc1_pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "tdc1_pll_status_i" LOC = "E9";
NET "tdc1_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "tdc1_pll_sdi_o" LOC = "M13";
NET "tdc1_pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_start_from_fpga_o" LOC = "F9";
NET "tdc1_start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[27]" LOC = "E17";
NET "tdc1_data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[26]" LOC = "F17";
NET "tdc1_data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[25]" LOC = "F18";
NET "tdc1_data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[24]" LOC = "G18";
NET "tdc1_data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[23]" LOC = "F20";
NET "tdc1_data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[22]" LOC = "G20";
NET "tdc1_data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[21]" LOC = "E21";
NET "tdc1_data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[20]" LOC = "F21";
NET "tdc1_data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[19]" LOC = "K21";
NET "tdc1_data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[18]" LOC = "L21";
NET "tdc1_data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[17]" LOC = "L20";
NET "tdc1_data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[16]" LOC = "M20";
NET "tdc1_data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[15]" LOC = "F22";
NET "tdc1_data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[14]" LOC = "G22";
NET "tdc1_data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[13]" LOC = "L19";
NET "tdc1_data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[12]" LOC = "M19";
NET "tdc1_data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[11]" LOC = "E23";
NET "tdc1_data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[10]" LOC = "F23";
NET "tdc1_data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[9]" LOC = "A25";
NET "tdc1_data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[8]" LOC = "B25";
NET "tdc1_data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[7]" LOC = "G21";
NET "tdc1_data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[6]" LOC = "C24";
NET "tdc1_data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[5]" LOC = "H21";
NET "tdc1_data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[4]" LOC = "D24";
NET "tdc1_data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[3]" LOC = "D25";
NET "tdc1_data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[2]" LOC = "E25";
NET "tdc1_data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[1]" LOC = "H22";
NET "tdc1_data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "tdc1_data_bus_io[0]" LOC = "J22";
NET "tdc1_data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "tdc1_address_o[3]" LOC = "F14";
NET "tdc1_address_o[3]" IOSTANDARD = "LVCMOS25";
NET "tdc1_address_o[2]" LOC = "G14";
NET "tdc1_address_o[2]" IOSTANDARD = "LVCMOS25";
NET "tdc1_address_o[1]" LOC = "H14";
NET "tdc1_address_o[1]" IOSTANDARD = "LVCMOS25";
NET "tdc1_address_o[0]" LOC = "J14";
NET "tdc1_address_o[0]" IOSTANDARD = "LVCMOS25";
NET "tdc1_oe_n_o" LOC = "G12";
NET "tdc1_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_rd_n_o" LOC = "A15";
NET "tdc1_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_wr_n_o" LOC = "B15";
NET "tdc1_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_enable_inputs_o" LOC = "J12";
NET "tdc1_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "tdc1_onewire_b" LOC = "H12";
NET "tdc1_onewire_b" IOSTANDARD = "LVCMOS25";
NET "tdc1_acam_refclk_p_i" LOC = H15;
NET "tdc1_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "tdc1_acam_refclk_n_i" LOC = G15;
NET "tdc1_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "tdc1_125m_clk_p_i" LOC = E16;
NET "tdc1_125m_clk_p_i" IOSTANDARD = LVDS_25;
NET "tdc1_125m_clk_n_i" LOC = D16;
NET "tdc1_125m_clk_n_i" IOSTANDARD = LVDS_25;
NET "tdc1_led_trig1_o" LOC = H13;
NET "tdc1_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig2_o" LOC = H11;
NET "tdc1_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig3_o" LOC = G11;
NET "tdc1_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_1_o" LOC = C16;
NET "tdc1_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_2_o" LOC = A16;
NET "tdc1_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "tdc1_ef1_i" LOC = F19;
NET "tdc1_ef1_i" IOSTANDARD = LVCMOS25;
NET "tdc1_ef2_i" LOC = E19;
NET "tdc1_ef2_i" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_3_o" LOC = F15;
NET "tdc1_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_4_o" LOC = E15;
NET "tdc1_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_5_o" LOC = F13;
NET "tdc1_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_status_o" LOC = E13;
NET "tdc1_led_status_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig4_o" LOC = L11;
NET "tdc1_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig5_o" LOC = K11;
NET "tdc1_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_sclk_o" LOC = M15;
NET "tdc1_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_dac_sync_n_o" LOC = K15;
NET "tdc1_pll_dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_cs_n_o" LOC = L14;
NET "tdc1_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_cs_n_o" LOC = K14;
NET "tdc1_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_err_flag_i" LOC = H16;
NET "tdc1_err_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc1_int_flag_i" LOC = G16;
NET "tdc1_int_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc1_start_dis_o" LOC = F11;
NET "tdc1_start_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc1_stop_dis_o" LOC = E11;
NET "tdc1_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_sdo_i" LOC = L13;
NET "tdc1_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_status_i" LOC = E9;
NET "tdc1_pll_status_i" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_sdi_o" LOC = M13;
NET "tdc1_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "tdc1_start_from_fpga_o" LOC = F9;
NET "tdc1_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[27]" LOC = E17;
NET "tdc1_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[26]" LOC = F17;
NET "tdc1_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[25]" LOC = F18;
NET "tdc1_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[24]" LOC = G18;
NET "tdc1_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[23]" LOC = F20;
NET "tdc1_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[22]" LOC = G20;
NET "tdc1_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[21]" LOC = E21;
NET "tdc1_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[20]" LOC = F21;
NET "tdc1_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[19]" LOC = K21;
NET "tdc1_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[18]" LOC = L21;
NET "tdc1_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[17]" LOC = L20;
NET "tdc1_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[16]" LOC = M20;
NET "tdc1_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[15]" LOC = F22;
NET "tdc1_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[14]" LOC = G22;
NET "tdc1_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[13]" LOC = L19;
NET "tdc1_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[12]" LOC = M19;
NET "tdc1_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[11]" LOC = E23;
NET "tdc1_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[10]" LOC = F23;
NET "tdc1_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[9]" LOC = A25;
NET "tdc1_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[8]" LOC = B25;
NET "tdc1_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[7]" LOC = G21;
NET "tdc1_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[6]" LOC = C24;
NET "tdc1_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[5]" LOC = H21;
NET "tdc1_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[4]" LOC = D24;
NET "tdc1_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[3]" LOC = D25;
NET "tdc1_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[2]" LOC = E25;
NET "tdc1_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[1]" LOC = H22;
NET "tdc1_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[0]" LOC = J22;
NET "tdc1_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[3]" LOC = F14;
NET "tdc1_address_o[3]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[2]" LOC = G14;
NET "tdc1_address_o[2]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[1]" LOC = H14;
NET "tdc1_address_o[1]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[0]" LOC = J14;
NET "tdc1_address_o[0]" IOSTANDARD = LVCMOS25;
NET "tdc1_oe_n_o" LOC = G12;
NET "tdc1_oe_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_rd_n_o" LOC = A15;
NET "tdc1_rd_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_wr_n_o" LOC = B15;
NET "tdc1_wr_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_enable_inputs_o" LOC = J12;
NET "tdc1_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "tdc1_onewire_b" LOC = H12;
NET "tdc1_onewire_b" IOSTANDARD = LVCMOS25;
#----------------------------------------
# FMC2
#----------------------------------------
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 1
NET "tdc2_acam_refclk_p_i" LOC = "AF16";
NET "tdc2_acam_refclk_p_i" IOSTANDARD = "LVDS_25";
NET "tdc2_acam_refclk_n_i" LOC = "AG16";
NET "tdc2_acam_refclk_n_i" IOSTANDARD = "LVDS_25";
NET "tdc2_125m_clk_p_i" LOC = "AH16";
NET "tdc2_125m_clk_p_i" IOSTANDARD = "LVDS_25";
NET "tdc2_125m_clk_n_i" LOC = "AK16";
NET "tdc2_125m_clk_n_i" IOSTANDARD = "LVDS_25";
NET "tdc2_led_trig1_o" LOC = "Y20";
NET "tdc2_led_trig1_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_led_trig2_o" LOC = "W19";
NET "tdc2_led_trig2_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_led_trig3_o" LOC = "Y19";
NET "tdc2_led_trig3_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_term_en_1_o" LOC = "AJ17";
NET "tdc2_term_en_1_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_term_en_2_o" LOC = "AK17";
NET "tdc2_term_en_2_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_ef1_i" LOC = "AB14";
NET "tdc2_ef1_i" IOSTANDARD = "LVCMOS25";
NET "tdc2_ef2_i" LOC = "AC14";
NET "tdc2_ef2_i" IOSTANDARD = "LVCMOS25";
NET "tdc2_term_en_3_o" LOC = "AE19";
NET "tdc2_term_en_3_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_term_en_4_o" LOC = "AF19";
NET "tdc2_term_en_4_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_term_en_5_o" LOC = "AE24";
NET "tdc2_term_en_5_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_led_status_o" LOC = "AF24";
NET "tdc2_led_status_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_led_trig4_o" LOC = "Y21";
NET "tdc2_led_trig4_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_led_trig5_o" LOC = "AA21";
NET "tdc2_led_trig5_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_pll_sclk_o" LOC = "AF25";
NET "tdc2_pll_sclk_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_pll_dac_sync_n_o" LOC = "AG25";
NET "tdc2_pll_dac_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_pll_cs_n_o" LOC = "AC19";
NET "tdc2_pll_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_cs_n_o" LOC = "AD19";
NET "tdc2_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_err_flag_i" LOC = "Y17";
NET "tdc2_err_flag_i" IOSTANDARD = "LVCMOS25";
NET "tdc2_int_flag_i" LOC = "AA17";
NET "tdc2_int_flag_i" IOSTANDARD = "LVCMOS25";
NET "tdc2_start_dis_o" LOC = "AB17";
NET "tdc2_start_dis_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_stop_dis_o" LOC = "AD17";
NET "tdc2_stop_dis_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_pll_sdo_i" LOC = "AC20";
NET "tdc2_pll_sdo_i" IOSTANDARD = "LVCMOS25";
NET "tdc2_pll_status_i" LOC = "AD24";
NET "tdc2_pll_status_i" IOSTANDARD = "LVCMOS25";
NET "tdc2_pll_sdi_o" LOC = "AB20";
NET "tdc2_pll_sdi_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_start_from_fpga_o" LOC = "AC24";
NET "tdc2_start_from_fpga_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[27]" LOC = "AA15";
NET "tdc2_data_bus_io[27]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[26]" LOC = "Y15";
NET "tdc2_data_bus_io[26]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[25]" LOC = "AD15";
NET "tdc2_data_bus_io[25]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[24]" LOC = "AC15";
NET "tdc2_data_bus_io[24]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[23]" LOC = "AB16";
NET "tdc2_data_bus_io[23]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[22]" LOC = "Y16";
NET "tdc2_data_bus_io[22]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[21]" LOC = "AF15";
NET "tdc2_data_bus_io[21]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[20]" LOC = "AE15";
NET "tdc2_data_bus_io[20]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[19]" LOC = "AA14";
NET "tdc2_data_bus_io[19]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[18]" LOC = "Y14";
NET "tdc2_data_bus_io[18]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[17]" LOC = "Y13";
NET "tdc2_data_bus_io[17]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[16]" LOC = "W14";
NET "tdc2_data_bus_io[16]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[15]" LOC = "AE12";
NET "tdc2_data_bus_io[15]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[14]" LOC = "AD12";
NET "tdc2_data_bus_io[14]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[13]" LOC = "AF11";
NET "tdc2_data_bus_io[13]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[12]" LOC = "AE11";
NET "tdc2_data_bus_io[12]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[11]" LOC = "AC12";
NET "tdc2_data_bus_io[11]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[10]" LOC = "AB12";
NET "tdc2_data_bus_io[10]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[9]" LOC = "AE10";
NET "tdc2_data_bus_io[9]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[8]" LOC = "AD10";
NET "tdc2_data_bus_io[8]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[7]" LOC = "AH8";
NET "tdc2_data_bus_io[7]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[6]" LOC = "AK15";
NET "tdc2_data_bus_io[6]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[5]" LOC = "AG8";
NET "tdc2_data_bus_io[5]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[4]" LOC = "AJ15";
NET "tdc2_data_bus_io[4]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[3]" LOC = "AF13";
NET "tdc2_data_bus_io[3]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[2]" LOC = "AE13";
NET "tdc2_data_bus_io[2]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[1]" LOC = "AD11";
NET "tdc2_data_bus_io[1]" IOSTANDARD = "LVCMOS25";
NET "tdc2_data_bus_io[0]" LOC = "AC11";
NET "tdc2_data_bus_io[0]" IOSTANDARD = "LVCMOS25";
NET "tdc2_address_o[3]" LOC = "AF23";
NET "tdc2_address_o[3]" IOSTANDARD = "LVCMOS25";
NET "tdc2_address_o[2]" LOC = "AE23";
NET "tdc2_address_o[2]" IOSTANDARD = "LVCMOS25";
NET "tdc2_address_o[1]" LOC = "AF21";
NET "tdc2_address_o[1]" IOSTANDARD = "LVCMOS25";
NET "tdc2_address_o[0]" LOC = "AE21";
NET "tdc2_address_o[0]" IOSTANDARD = "LVCMOS25";
NET "tdc2_oe_n_o" LOC = "AD22";
NET "tdc2_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_rd_n_o" LOC = "AD16";
NET "tdc2_rd_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_wr_n_o" LOC = "AC16";
NET "tdc2_wr_n_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_enable_inputs_o" LOC = "AA19";
NET "tdc2_enable_inputs_o" IOSTANDARD = "LVCMOS25";
NET "tdc2_onewire_b" LOC = "AB19";
NET "tdc2_onewire_b" IOSTANDARD = "LVCMOS25";
NET "tdc2_acam_refclk_p_i" LOC = AF16;
NET "tdc2_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "tdc2_acam_refclk_n_i" LOC = AG16;
NET "tdc2_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "tdc2_125m_clk_p_i" LOC = AH16;
NET "tdc2_125m_clk_p_i" IOSTANDARD = LVDS_25;
NET "tdc2_125m_clk_n_i" LOC = AK16;
NET "tdc2_125m_clk_n_i" IOSTANDARD = LVDS_25;
NET "tdc2_led_trig1_o" LOC = Y20;
NET "tdc2_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig2_o" LOC = W19;
NET "tdc2_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig3_o" LOC = Y19;
NET "tdc2_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_1_o" LOC = AJ17;
NET "tdc2_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_2_o" LOC = AK17;
NET "tdc2_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "tdc2_ef1_i" LOC = AB14;
NET "tdc2_ef1_i" IOSTANDARD = LVCMOS25;
NET "tdc2_ef2_i" LOC = AC14;
NET "tdc2_ef2_i" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_3_o" LOC = AE19;
NET "tdc2_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_4_o" LOC = AF19;
NET "tdc2_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_5_o" LOC = AE24;
NET "tdc2_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_status_o" LOC = AF24;
NET "tdc2_led_status_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig4_o" LOC = Y21;
NET "tdc2_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig5_o" LOC = AA21;
NET "tdc2_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_sclk_o" LOC = AF25;
NET "tdc2_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_dac_sync_n_o" LOC = AG25;
NET "tdc2_pll_dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_cs_n_o" LOC = AC19;
NET "tdc2_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_cs_n_o" LOC = AD19;
NET "tdc2_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_err_flag_i" LOC = Y17;
NET "tdc2_err_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc2_int_flag_i" LOC = AA17;
NET "tdc2_int_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc2_start_dis_o" LOC = AB17;
NET "tdc2_start_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc2_stop_dis_o" LOC = AD17;
NET "tdc2_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_sdo_i" LOC = AC20;
NET "tdc2_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_status_i" LOC = AD24;
NET "tdc2_pll_status_i" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_sdi_o" LOC = AB20;
NET "tdc2_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "tdc2_start_from_fpga_o" LOC = AC24;
NET "tdc2_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[27]" LOC = AA15;
NET "tdc2_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[26]" LOC = Y15;
NET "tdc2_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[25]" LOC = AD15;
NET "tdc2_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[24]" LOC = AC15;
NET "tdc2_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[23]" LOC = AB16;
NET "tdc2_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[22]" LOC = Y16;
NET "tdc2_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[21]" LOC = AF15;
NET "tdc2_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[20]" LOC = AE15;
NET "tdc2_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[19]" LOC = AA14;
NET "tdc2_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[18]" LOC = Y14;
NET "tdc2_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[17]" LOC = Y13;
NET "tdc2_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[16]" LOC = W14;
NET "tdc2_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[15]" LOC = AE12;
NET "tdc2_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[14]" LOC = AD12;
NET "tdc2_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[13]" LOC = AF11;
NET "tdc2_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[12]" LOC = AE11;
NET "tdc2_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[11]" LOC = AC12;
NET "tdc2_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[10]" LOC = AB12;
NET "tdc2_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[9]" LOC = AE10;
NET "tdc2_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[8]" LOC = AD10;
NET "tdc2_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[7]" LOC = AH8;
NET "tdc2_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[6]" LOC = AK15;
NET "tdc2_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[5]" LOC = AG8;
NET "tdc2_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[4]" LOC = AJ15;
NET "tdc2_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[3]" LOC = AF13;
NET "tdc2_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[2]" LOC = AE13;
NET "tdc2_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[1]" LOC = AD11;
NET "tdc2_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[0]" LOC = AC11;
NET "tdc2_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[3]" LOC = AF23;
NET "tdc2_address_o[3]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[2]" LOC = AE23;
NET "tdc2_address_o[2]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[1]" LOC = AF21;
NET "tdc2_address_o[1]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[0]" LOC = AE21;
NET "tdc2_address_o[0]" IOSTANDARD = LVCMOS25;
NET "tdc2_oe_n_o" LOC = AD22;
NET "tdc2_oe_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_rd_n_o" LOC = AD16;
NET "tdc2_rd_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_wr_n_o" LOC = AC16;
NET "tdc2_wr_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_enable_inputs_o" LOC = AA19;
NET "tdc2_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "tdc2_onewire_b" LOC = AB19;
NET "tdc2_onewire_b" IOSTANDARD = LVCMOS25;
#----------------------------------------
# SFP slot
#----------------------------------------
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_p_i" TNM_NET = clk_125m_gtp_p_i;
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50%;
NET "clk_125m_gtp_n_i" TNM_NET = "clk_125m_gtp_n_i";
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50 %;
NET "clk_125m_gtp_p_i" TNM_NET = "clk_125m_gtp_p_i";
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50 %;
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
......@@ -570,13 +569,13 @@ NET "sfp_mod_def2_b" LOC = AA24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
#NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
......@@ -585,20 +584,20 @@ NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
NET "pll20dac_din_o" IOSTANDARD = LVCMOS33;
NET "pll20dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll20dac_sync_n_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_din_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sync_n_o" IOSTANDARD = LVCMOS33;
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
NET "uart_txd_o" IOSTANDARD = LVCMOS33;
NET "uart_rxd_i" IOSTANDARD = LVCMOS33;
#----------------------------------------
......@@ -607,8 +606,8 @@ NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
# SVEC VCXO clock/reset
NET "clk_20m_vcxo_i" LOC = V26;
NET "por_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" IOSTANDARD="LVCMOS33";
NET "por_n_i" IOSTANDARD="LVCMOS33";
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
NET "por_n_i" IOSTANDARD = LVCMOS33;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
# 62.5MHz Xilinx PLL clock/reset
......@@ -624,36 +623,128 @@ NET "tdc2_125m_clk" TNM_NET = "tdc2_125m_clk";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2013/07/19
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "tdc1_125m_clk_n_i" TNM_NET = tdc1_125m_clk_n_i;
TIMESPEC TS_tdc1_tdc_125m_clk_n_i = PERIOD "tdc1_125m_clk_n_i" 8 ns HIGH 50%;
NET "tdc1_125m_clk_p_i" TNM_NET = tdc1_125m_clk_p_i;
TIMESPEC TS_tdc1_125m_clk_p_i = PERIOD "tdc1_125m_clk_p_i" 8 ns HIGH 50%;
NET "tdc2_125m_clk_p_i" TNM_NET = tdc2_125m_clk_p_i;
TIMESPEC TS_tdc2_tdc_125m_clk_p_i = PERIOD "tdc2_125m_clk_p_i" 8 ns HIGH 50%;
NET "tdc2_125m_clk_n_i" TNM_NET = tdc2_125m_clk_n_i;
TIMESPEC TS_tdc2_tdc_125m_clk_n_i = PERIOD "tdc2_125m_clk_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50 %;
NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50 %;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50 %;
NET "tdc1_125m_clk_n_i" TNM_NET = "tdc1_125m_clk_n_i";
TIMESPEC TS_tdc1_tdc_125m_clk_n_i = PERIOD "tdc1_125m_clk_n_i" 8 ns HIGH 50 %;
NET "tdc1_125m_clk_p_i" TNM_NET = "tdc1_125m_clk_p_i";
TIMESPEC TS_tdc1_125m_clk_p_i = PERIOD "tdc1_125m_clk_p_i" 8 ns HIGH 50 %;
NET "tdc2_125m_clk_p_i" TNM_NET = "tdc2_125m_clk_p_i";
TIMESPEC TS_tdc2_tdc_125m_clk_p_i = PERIOD "tdc2_125m_clk_p_i" 8 ns HIGH 50 %;
NET "tdc2_125m_clk_n_i" TNM_NET = "tdc2_125m_clk_n_i";
TIMESPEC TS_tdc2_tdc_125m_clk_n_i = PERIOD "tdc2_125m_clk_n_i" 8 ns HIGH 50 %;
# TS_IGNORE
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc1_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc1_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc1_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc1_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_62m5_sys" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2015/03/31
NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50 %;
# PlanAhead Generated miscellaneous constraints
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
# PlanAhead Generated IO constraints
NET "tdc1_address_o[3]" SLEW = FAST;
NET "tdc1_address_o[2]" SLEW = FAST;
NET "tdc1_address_o[1]" SLEW = FAST;
NET "tdc1_address_o[0]" SLEW = FAST;
NET "tdc1_data_bus_io[27]" SLEW = FAST;
NET "tdc1_data_bus_io[26]" SLEW = FAST;
NET "tdc1_data_bus_io[25]" SLEW = FAST;
NET "tdc1_data_bus_io[24]" SLEW = FAST;
NET "tdc1_data_bus_io[23]" SLEW = FAST;
NET "tdc1_data_bus_io[22]" SLEW = FAST;
NET "tdc1_data_bus_io[21]" SLEW = FAST;
NET "tdc1_data_bus_io[20]" SLEW = FAST;
NET "tdc1_data_bus_io[19]" SLEW = FAST;
NET "tdc1_data_bus_io[18]" SLEW = FAST;
NET "tdc1_data_bus_io[17]" SLEW = FAST;
NET "tdc1_data_bus_io[16]" SLEW = FAST;
NET "tdc1_data_bus_io[15]" SLEW = FAST;
NET "tdc1_data_bus_io[14]" SLEW = FAST;
NET "tdc1_data_bus_io[13]" SLEW = FAST;
NET "tdc1_data_bus_io[12]" SLEW = FAST;
NET "tdc1_data_bus_io[11]" SLEW = FAST;
NET "tdc1_data_bus_io[10]" SLEW = FAST;
NET "tdc1_data_bus_io[9]" SLEW = FAST;
NET "tdc1_data_bus_io[8]" SLEW = FAST;
NET "tdc1_data_bus_io[7]" SLEW = FAST;
NET "tdc1_data_bus_io[6]" SLEW = FAST;
NET "tdc1_data_bus_io[5]" SLEW = FAST;
NET "tdc1_data_bus_io[4]" SLEW = FAST;
NET "tdc1_data_bus_io[3]" SLEW = FAST;
NET "tdc1_data_bus_io[2]" SLEW = FAST;
NET "tdc1_data_bus_io[1]" SLEW = FAST;
NET "tdc1_data_bus_io[0]" SLEW = FAST;
NET "tdc2_address_o[3]" SLEW = FAST;
NET "tdc2_address_o[2]" SLEW = FAST;
NET "tdc2_address_o[1]" SLEW = FAST;
NET "tdc2_address_o[0]" SLEW = FAST;
NET "tdc2_data_bus_io[27]" SLEW = FAST;
NET "tdc2_data_bus_io[26]" SLEW = FAST;
NET "tdc2_data_bus_io[25]" SLEW = FAST;
NET "tdc2_data_bus_io[24]" SLEW = FAST;
NET "tdc2_data_bus_io[23]" SLEW = FAST;
NET "tdc2_data_bus_io[22]" SLEW = FAST;
NET "tdc2_data_bus_io[21]" SLEW = FAST;
NET "tdc2_data_bus_io[20]" SLEW = FAST;
NET "tdc2_data_bus_io[19]" SLEW = FAST;
NET "tdc2_data_bus_io[18]" SLEW = FAST;
NET "tdc2_data_bus_io[17]" SLEW = FAST;
NET "tdc2_data_bus_io[16]" SLEW = FAST;
NET "tdc2_data_bus_io[15]" SLEW = FAST;
NET "tdc2_data_bus_io[14]" SLEW = FAST;
NET "tdc2_data_bus_io[13]" SLEW = FAST;
NET "tdc2_data_bus_io[12]" SLEW = FAST;
NET "tdc2_data_bus_io[11]" SLEW = FAST;
NET "tdc2_data_bus_io[10]" SLEW = FAST;
NET "tdc2_data_bus_io[9]" SLEW = FAST;
NET "tdc2_data_bus_io[8]" SLEW = FAST;
NET "tdc2_data_bus_io[7]" SLEW = FAST;
NET "tdc2_data_bus_io[6]" SLEW = FAST;
NET "tdc2_data_bus_io[5]" SLEW = FAST;
NET "tdc2_data_bus_io[4]" SLEW = FAST;
NET "tdc2_data_bus_io[3]" SLEW = FAST;
NET "tdc2_data_bus_io[2]" SLEW = FAST;
NET "tdc2_data_bus_io[1]" SLEW = FAST;
NET "tdc2_data_bus_io[0]" SLEW = FAST;
hdl/top/svec/wr_svec_tdc.vhd
View file @ 92b7f5e7
......@@ -376,16 +376,16 @@ architecture rtl of wr_svec_tdc is
constant c_SLAVE_WRCORE : integer := 4; -- White Rabbit PTP core
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_FMC_TDC2_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_FMC_TDC2_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device (c_SVEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"),
2 => f_sdb_embed_bridge (c_FMC_TDC1_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_FMC_TDC2_SDB_BRIDGE, x"00060000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
(0 => f_sdb_embed_device (c_SVEC_INFO_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00002000"),
2 => f_sdb_embed_bridge (c_FMC_TDC1_SDB_BRIDGE, x"00010000"),
3 => f_sdb_embed_bridge (c_FMC_TDC2_SDB_BRIDGE, x"00020000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00040000"),
5 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
......@@ -393,8 +393,8 @@ architecture rtl of wr_svec_tdc is
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00052000",
1 => x"00072000");
(0 => x"00013000",
1 => x"00023000");
---------------------------------------------------------------------------------------------------
-- Signals --
......@@ -498,9 +498,6 @@ architecture rtl of wr_svec_tdc is
signal led_state : std_logic_vector(15 downto 0);
signal tdc1_ef, tdc2_ef, led_tdc1_ef : std_logic;
signal led_tdc2_ef, led_vme_access : std_logic;
signal led_clk_62m5_divider : unsigned(22 downto 0);
signal led_clk_62m5_aux : std_logic_vector(7 downto 0);
signal led_clk_62m5 : std_logic;
signal wrabbit_led_red, wrabbit_led_green : std_logic;
--=================================================================================================
......@@ -524,7 +521,7 @@ begin
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 20 MHz x 50 = 1 GHz
CLKFBOUT_MULT => 8, -- 125 MHz x 8 = 1 GHz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
......@@ -535,7 +532,7 @@ begin
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_sys_fb,
......@@ -548,7 +545,7 @@ begin
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_sys_fb,
CLKIN => clk_20m_vcxo_buf);
CLKIN => clk_125m_pllref);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
port map
......@@ -999,10 +996,87 @@ begin
tdc1_scl_in <= tdc1_scl_b;
tdc1_sda_in <= tdc1_sda_b;
cmp_tdc_mezzanine_2: fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false )
port map (
clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_n_sys,
rst_n_a_i => tdc2_soft_rst_n,
pll_sclk_o => tdc2_pll_sclk_o,
pll_sdi_o => tdc2_pll_sdi_o,
pll_cs_o => tdc2_pll_cs_n_o,
pll_dac_sync_o => tdc2_pll_dac_sync_n_o,
pll_sdo_i => tdc2_pll_sdo_i,
pll_status_i => tdc2_pll_status_i,
tdc_clk_125m_p_i => tdc2_125m_clk_p_i,
tdc_clk_125m_n_i => tdc2_125m_clk_n_i,
acam_refclk_p_i => tdc2_acam_refclk_p_i,
acam_refclk_n_i => tdc2_acam_refclk_n_i,
start_from_fpga_o => tdc2_start_from_fpga_o,
err_flag_i => tdc2_err_flag_i,
int_flag_i => tdc2_int_flag_i,
start_dis_o => tdc2_start_dis_o,
stop_dis_o => tdc2_stop_dis_o,
data_bus_io => tdc2_data_bus_io,
address_o => tdc2_address_o,
cs_n_o => tdc2_cs_n_o,
oe_n_o => tdc2_oe_n_o,
rd_n_o => tdc2_rd_n_o,
wr_n_o => tdc2_wr_n_o,
ef1_i => tdc2_ef1_i,
ef2_i => tdc2_ef2_i,
enable_inputs_o => tdc2_enable_inputs_o,
term_en_1_o => tdc2_term_en_1_o,
term_en_2_o => tdc2_term_en_2_o,
term_en_3_o => tdc2_term_en_3_o,
term_en_4_o => tdc2_term_en_4_o,
term_en_5_o => tdc2_term_en_5_o,
tdc_led_status_o => tdc2_led_status_o,
tdc_led_trig1_o => tdc2_led_trig1_o,
tdc_led_trig2_o => tdc2_led_trig2_o,
tdc_led_trig3_o => tdc2_led_trig3_o,
tdc_led_trig4_o => tdc2_led_trig4_o,
tdc_led_trig5_o => tdc2_led_trig5_o,
tdc_in_fpga_1_i => tdc2_in_fpga_1_i,
tdc_in_fpga_2_i => tdc2_in_fpga_2_i,
tdc_in_fpga_3_i => tdc2_in_fpga_3_i,
tdc_in_fpga_4_i => tdc2_in_fpga_4_i,
tdc_in_fpga_5_i => tdc2_in_fpga_5_i,
mezz_scl_i => tdc2_scl_in,
mezz_sda_i => tdc2_sda_in,
mezz_scl_o => tdc2_scl_oen,
mezz_sda_o => tdc2_sda_oen,
mezz_one_wire_b => tdc2_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
tm_cycles_i => tm_cycles,
tm_tai_i => tm_utc,
tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
tm_clk_aux_locked_i => tm_clk_aux_locked(1),
tm_clk_dmtd_locked_i => '1',
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr_p(1),
slave_i => cnx_master_out(c_SLAVE_TDC1),
slave_o => cnx_master_in(c_SLAVE_TDC1),
irq_o => tdc2_irq,
clk_125m_tdc_o => tdc2_125m_clk);
tdc2_scl_b <= '0' when (tdc2_scl_oen = '0') else 'Z';
tdc2_sda_b <= '0' when (tdc2_sda_oen = '0') else 'Z';
tdc2_scl_in <= tdc2_scl_b;
tdc2_sda_in <= tdc2_sda_b;
---------------------------------------------------------------------------------------------------
-- VECTOR INTERRUPTS CONTROLLER --
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
cmp_irq_vic : xwb_vic
generic map
......
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