Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit 6ed2a256 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

[hdl] make pulse width filtering optional

parent 97684cd3
Show whitespace changes
Inline Side-by-side
Showing with 112 additions and 57 deletions
hdl/rtl/fmc_tdc_core.vhd
View file @ 6ed2a256
......@@ -153,9 +153,16 @@ entity fmc_tdc_core is
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simulation : boolean := false;
-- Enable filtering based on pulse width. This will have the following effects:
-- * Suppress theforwarding of negative slope timestamps.
-- * Delay the forwarding of timestamps until after the falling edge timestamp.
-- Once enabled, all pulses wider than 1 second or narrower than
-- g_pulse_width_filter_min will be dropped.
g_pulse_width_filter : boolean := true;
-- In 8ns ticks.
g_pulse_width_filter_min : natural := 12;
g_with_dma_readout : boolean := false;
g_with_fifo_readout : boolean := false); -- this generic is set to TRUE
-- when instantiated in a test-bench
g_with_fifo_readout : boolean := false);
port
(
clk_sys_i : in std_logic;
......@@ -536,6 +543,9 @@ begin
U_FilterAndConvert : entity work.timestamp_convert_filter
generic map (
g_pulse_width_filter => g_pulse_width_filter,
g_pulse_width_filter_min => g_pulse_width_filter_min)
port map (
clk_tdc_i => clk_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 6ed2a256
......@@ -110,6 +110,14 @@ entity fmc_tdc_mezzanine is
g_span : integer := 32;
g_width : integer := 32;
g_simulation : boolean := false;
-- Enable filtering based on pulse width. This will have the following effects:
-- * Suppress theforwarding of negative slope timestamps.
-- * Delay the forwarding of timestamps until after the falling edge timestamp.
-- Once enabled, all pulses wider than 1 second or narrower than
-- g_pulse_width_filter_min will be dropped.
g_pulse_width_filter : boolean := true;
-- In 8ns ticks.
g_pulse_width_filter_min : natural := 12;
g_use_dma_readout : boolean := true;
g_use_fifo_readout : boolean := true;
g_use_fake_timestamps_for_sim : boolean := false);
......@@ -329,6 +337,8 @@ begin
(g_span => g_span,
g_width => g_width,
g_simulation => g_simulation,
g_pulse_width_filter => g_pulse_width_filter,
g_pulse_width_filter_min => g_pulse_width_filter_min,
g_with_dma_readout => g_use_dma_readout,
g_with_fifo_readout => g_use_fifo_readout)
port map
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ 6ed2a256
......@@ -132,6 +132,14 @@ entity fmc_tdc_wrapper is
g_simulation : boolean := false;
-- implement direct TDC timestamp readout FIFO, used in the WR Node projects
g_with_direct_readout : boolean := false;
-- Enable filtering based on pulse width. This will have the following effects:
-- * Suppress theforwarding of negative slope timestamps.
-- * Delay the forwarding of timestamps until after the falling edge timestamp.
-- Once enabled, all pulses wider than 1 second or narrower than
-- g_pulse_width_filter_min will be dropped.
g_pulse_width_filter : boolean := true;
-- In 8ns ticks.
g_pulse_width_filter_min : natural := 12;
g_use_dma_readout : boolean := false;
g_use_fifo_readout : boolean := false;
g_use_fake_timestamps_for_sim : boolean := false
......@@ -404,6 +412,8 @@ begin
(g_span => 32,
g_width => 32,
g_simulation => g_simulation,
g_pulse_width_filter => g_pulse_width_filter,
g_pulse_width_filter_min => g_pulse_width_filter_min,
g_use_fifo_readout => g_use_fifo_readout,
g_use_dma_readout => g_use_dma_readout,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
......
hdl/rtl/timestamp_convert_filter.vhd
View file @ 6ed2a256
......@@ -8,6 +8,15 @@ use work.gencores_pkg.all;
use work.genram_pkg.all;
entity timestamp_convert_filter is
generic (
-- Enable filtering based on pulse width. This will have the following effects:
-- * Suppress theforwarding of negative slope timestamps.
-- * Delay the forwarding of timestamps until after the falling edge timestamp.
-- Once enabled, all pulses wider than 1 second or narrower than
-- g_PULSE_WIDTH_FILTER_MIN will be dropped.
g_PULSE_WIDTH_FILTER : boolean := TRUE;
-- In 8ns ticks.
g_PULSE_WIDTH_FILTER_MIN : natural := 12);
port (
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
......@@ -37,13 +46,10 @@ end timestamp_convert_filter;
architecture rtl of timestamp_convert_filter is
constant c_MIN_PULSE_WIDTH_TICKS : integer := 12; -- 12 * 8 ns = 96 ns
constant c_FINE_SF : unsigned(17 downto 0) := to_unsigned(84934, 18);
constant c_FINE_SHIFT : integer := 11;
type t_channel_state is record
expected_edge : std_logic;
last_ts : t_tdc_timestamp;
last_valid : std_logic;
seq : unsigned(31 downto 0);
......@@ -211,12 +217,12 @@ architecture rtl of timestamp_convert_filter is
gen_channels : for i in 0 to 4 generate
gen_with_pwidth_filter : if g_PULSE_WIDTH_FILTER generate
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i(i) = '0' then
ts_valid_preoffset(i) <= '0';
channels(i).expected_edge <= '1';
channels(i).s1_valid <= '0';
channels(i).s2_valid <= '0';
channels(i).last_valid <= '0';
......@@ -269,7 +275,26 @@ architecture rtl of timestamp_convert_filter is
end if;
end if;
end process;
end process p_fsm;
end generate gen_with_pwidth_filter;
gen_without_pwidth_filter : if not g_PULSE_WIDTH_FILTER generate
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i(i) = '0' then
ts_valid_preoffset(i) <= '0';
else
if s3_valid = '1' and unsigned(s3_channel) = i then
ts_valid_preoffset(i) <= '1';
ts_preoffset(i) <= s3_ts;
else
ts_valid_preoffset(i) <= '0';
end if;
end if;
end if;
end process p_fsm;
end generate gen_without_pwidth_filter;
U_Offset_Adder : entity work.tdc_ts_addsub
port map (
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment