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FMC TDC 1ns 5cha - Gateware
Commits
4d681a60
Commit
4d681a60
authored
Jan 17, 2017
by
Grzegorz Daniluk
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adding Xilinx ISE project file for SPEC
parent
1170651f
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1 changed file
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470 additions
and
469 deletions
+470
-469
wr_spec_tdc.xise
hdl/syn/spec/wr_spec_tdc.xise
+470
-469
No files found.
hdl/syn/spec/wr_spec_tdc.xise
View file @
4d681a60
...
...
@@ -9,7 +9,7 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-201
3
Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-201
2
Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
...
...
@@ -49,7 +49,7 @@
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...
...
@@ -132,7 +132,7 @@
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...
...
@@ -318,7 +318,7 @@
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...
...
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