Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC TDC 1ns 5cha - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC TDC 1ns 5cha - Gateware
Commits
3fdaa92b
Commit
3fdaa92b
authored
Apr 22, 2020
by
Evangelia Gousiou
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
wip testbench spec
parent
ac0bebbb
Show whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
274 additions
and
60 deletions
+274
-60
tdc_core_csr_wb.vh
hdl/testbench/include/tdc_core_csr_wb.vh
+92
-0
tdc_eic_wb_regs.vh
hdl/testbench/include/tdc_eic_wb_regs.vh
+84
-0
buildinfo_pkg.vhd
hdl/testbench/spec/buildinfo_pkg.vhd
+2
-2
main.sv
hdl/testbench/spec/main.sv
+96
-58
No files found.
hdl/testbench/include/tdc_core_csr_wb.vh
0 → 100644
View file @
3fdaa92b
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG0 8'h0
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG1 8'h4
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG2 8'h8
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG3 8'hc
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG4 8'h10
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG5 8'h14
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG6 8'h18
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG7 8'h1c
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG11 8'h2c
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG12 8'h30
`define ADDR_TDC_CORE_CSR_ACAM_CFG_REG14 8'h38
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG0 8'h40
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG1 8'h44
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG2 8'h48
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG3 8'h4c
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG4 8'h50
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG5 8'h54
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG6 8'h58
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG7 8'h5c
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG8 8'h60
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG9 8'h64
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG10 8'h68
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG11 8'h6c
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG12 8'h70
`define ADDR_TDC_CORE_CSR_ACAM_RD_CFG_REG14 8'h78
`define ADDR_TDC_CORE_CSR_STARTING_UTC 8'h80
`define ADDR_TDC_CORE_CSR_ENABLE 8'h84
`define TDC_CORE_CSR_ENABLE_CH1_TERM_OFFSET 0
`define TDC_CORE_CSR_ENABLE_CH1_TERM 32'h00000001
`define TDC_CORE_CSR_ENABLE_CH2_TERM_OFFSET 1
`define TDC_CORE_CSR_ENABLE_CH2_TERM 32'h00000002
`define TDC_CORE_CSR_ENABLE_CH3_TERM_OFFSET 2
`define TDC_CORE_CSR_ENABLE_CH3_TERM 32'h00000004
`define TDC_CORE_CSR_ENABLE_CH4_TERM_OFFSET 3
`define TDC_CORE_CSR_ENABLE_CH4_TERM 32'h00000008
`define TDC_CORE_CSR_ENABLE_CH5_TERM_OFFSET 4
`define TDC_CORE_CSR_ENABLE_CH5_TERM 32'h00000010
`define TDC_CORE_CSR_ENABLE_ACAM_ACQ_OFFSET 7
`define TDC_CORE_CSR_ENABLE_ACAM_ACQ 32'h00000080
`define ADDR_TDC_CORE_CSR_C000FFEE_BREAK 8'h8c
`define ADDR_TDC_CORE_CSR_IRQ_TSTAMP_THRESH 8'h90
`define ADDR_TDC_CORE_CSR_IRQ_TIME_THRESH 8'h94
`define ADDR_TDC_CORE_CSR_DAC_WORD 8'h98
`define ADDR_TDC_CORE_CSR_UTC 8'ha0
`define ADDR_TDC_CORE_CSR_CORE_STATUS 8'hac
`define ADDR_TDC_CORE_CSR_WR_STAT 8'hb0
`define TDC_CORE_CSR_WR_STAT_WITH_WR_CORE_OFFSET 0
`define TDC_CORE_CSR_WR_STAT_WITH_WR_CORE 32'h00000001
`define TDC_CORE_CSR_WR_STAT_LINK_UP_OFFSET 1
`define TDC_CORE_CSR_WR_STAT_LINK_UP 32'h00000002
`define TDC_CORE_CSR_WR_STAT_AUX_CLK_LOCKED_OFFSET 2
`define TDC_CORE_CSR_WR_STAT_AUX_CLK_LOCKED 32'h00000004
`define TDC_CORE_CSR_WR_STAT_TIME_VALID_OFFSET 3
`define TDC_CORE_CSR_WR_STAT_TIME_VALID 32'h00000008
`define TDC_CORE_CSR_WR_STAT_AUX_CLK_LOCK_EN_OFFSET 4
`define TDC_CORE_CSR_WR_STAT_AUX_CLK_LOCK_EN 32'h00000010
`define ADDR_TDC_CORE_CSR_WR_CTRL 8'hb4
`define TDC_CORE_CSR_WR_CTRL_EN_OFFSET 0
`define TDC_CORE_CSR_WR_CTRL_EN 32'h00000001
`define TDC_CORE_CSR_WR_CTRL_UNUSED_OFFSET 1
`define TDC_CORE_CSR_WR_CTRL_UNUSED 32'hfffffffe
`define ADDR_TDC_CORE_CSR_TEST0 8'hb8
`define TDC_CORE_CSR_TEST0_FAKE_TS_PERIOD_OFFSET 0
`define TDC_CORE_CSR_TEST0_FAKE_TS_PERIOD 32'h0fffffff
`define TDC_CORE_CSR_TEST0_FAKE_TS_CH_OFFSET 28
`define TDC_CORE_CSR_TEST0_FAKE_TS_CH 32'h70000000
`define TDC_CORE_CSR_TEST0_FAKE_TS_EN_OFFSET 31
`define TDC_CORE_CSR_TEST0_FAKE_TS_EN 32'h80000000
`define ADDR_TDC_CORE_CSR_TEST1 8'hbc
`define ADDR_TDC_CORE_CSR_CTRL 8'hfc
`define TDC_CORE_CSR_CTRL_ACTIVATE_ACQ_P_OFFSET 0
`define TDC_CORE_CSR_CTRL_ACTIVATE_ACQ_P 32'h00000001
`define TDC_CORE_CSR_CTRL_DEACTIVATE_ACQ_P_OFFSET 1
`define TDC_CORE_CSR_CTRL_DEACTIVATE_ACQ_P 32'h00000002
`define TDC_CORE_CSR_CTRL_LOAD_ACAM_CFG_P_OFFSET 2
`define TDC_CORE_CSR_CTRL_LOAD_ACAM_CFG_P 32'h00000004
`define TDC_CORE_CSR_CTRL_RD_ACAM_CFG_P_OFFSET 3
`define TDC_CORE_CSR_CTRL_RD_ACAM_CFG_P 32'h00000008
`define TDC_CORE_CSR_CTRL_RD_ACAM_STATUS_P_OFFSET 4
`define TDC_CORE_CSR_CTRL_RD_ACAM_STATUS_P 32'h00000010
`define TDC_CORE_CSR_CTRL_RD_ACAM_IFIFO1_P_OFFSET 5
`define TDC_CORE_CSR_CTRL_RD_ACAM_IFIFO1_P 32'h00000020
`define TDC_CORE_CSR_CTRL_RD_ACAM_IFIFO2_P_OFFSET 6
`define TDC_CORE_CSR_CTRL_RD_ACAM_IFIFO2_P 32'h00000040
`define TDC_CORE_CSR_CTRL_RD_ACAM_START01_P_OFFSET 7
`define TDC_CORE_CSR_CTRL_RD_ACAM_START01_P 32'h00000080
`define TDC_CORE_CSR_CTRL_RST_ACAM_P_OFFSET 8
`define TDC_CORE_CSR_CTRL_RST_ACAM_P 32'h00000100
`define TDC_CORE_CSR_CTRL_LOAD_UTC_P_OFFSET 9
`define TDC_CORE_CSR_CTRL_LOAD_UTC_P 32'h00000200
`define TDC_CORE_CSR_CTRL_LOAD_DAC_P_OFFSET 10
`define TDC_CORE_CSR_CTRL_LOAD_DAC_P 32'h00000400
hdl/testbench/include/tdc_eic_wb_regs.vh
0 → 100644
View file @
3fdaa92b
`define ADDR_TDC_EIC_EIC_IDR 6'h20
`define TDC_EIC_EIC_IDR_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_IDR_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_IDR_TDC_FIFO2_OFFSET 1
`define TDC_EIC_EIC_IDR_TDC_FIFO2 32'h00000002
`define TDC_EIC_EIC_IDR_TDC_FIFO3_OFFSET 2
`define TDC_EIC_EIC_IDR_TDC_FIFO3 32'h00000004
`define TDC_EIC_EIC_IDR_TDC_FIFO4_OFFSET 3
`define TDC_EIC_EIC_IDR_TDC_FIFO4 32'h00000008
`define TDC_EIC_EIC_IDR_TDC_FIFO5_OFFSET 4
`define TDC_EIC_EIC_IDR_TDC_FIFO5 32'h00000010
`define TDC_EIC_EIC_IDR_TDC_DMA1_OFFSET 5
`define TDC_EIC_EIC_IDR_TDC_DMA1 32'h00000020
`define TDC_EIC_EIC_IDR_TDC_DMA2_OFFSET 6
`define TDC_EIC_EIC_IDR_TDC_DMA2 32'h00000040
`define TDC_EIC_EIC_IDR_TDC_DMA3_OFFSET 7
`define TDC_EIC_EIC_IDR_TDC_DMA3 32'h00000080
`define TDC_EIC_EIC_IDR_TDC_DMA4_OFFSET 8
`define TDC_EIC_EIC_IDR_TDC_DMA4 32'h00000100
`define TDC_EIC_EIC_IDR_TDC_DMA5_OFFSET 9
`define TDC_EIC_EIC_IDR_TDC_DMA5 32'h00000200
`define ADDR_TDC_EIC_EIC_IER 6'h24
`define TDC_EIC_EIC_IER_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_IER_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_IER_TDC_FIFO2_OFFSET 1
`define TDC_EIC_EIC_IER_TDC_FIFO2 32'h00000002
`define TDC_EIC_EIC_IER_TDC_FIFO3_OFFSET 2
`define TDC_EIC_EIC_IER_TDC_FIFO3 32'h00000004
`define TDC_EIC_EIC_IER_TDC_FIFO4_OFFSET 3
`define TDC_EIC_EIC_IER_TDC_FIFO4 32'h00000008
`define TDC_EIC_EIC_IER_TDC_FIFO5_OFFSET 4
`define TDC_EIC_EIC_IER_TDC_FIFO5 32'h00000010
`define TDC_EIC_EIC_IER_TDC_DMA1_OFFSET 5
`define TDC_EIC_EIC_IER_TDC_DMA1 32'h00000020
`define TDC_EIC_EIC_IER_TDC_DMA2_OFFSET 6
`define TDC_EIC_EIC_IER_TDC_DMA2 32'h00000040
`define TDC_EIC_EIC_IER_TDC_DMA3_OFFSET 7
`define TDC_EIC_EIC_IER_TDC_DMA3 32'h00000080
`define TDC_EIC_EIC_IER_TDC_DMA4_OFFSET 8
`define TDC_EIC_EIC_IER_TDC_DMA4 32'h00000100
`define TDC_EIC_EIC_IER_TDC_DMA5_OFFSET 9
`define TDC_EIC_EIC_IER_TDC_DMA5 32'h00000200
`define ADDR_TDC_EIC_EIC_IMR 6'h28
`define TDC_EIC_EIC_IMR_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_IMR_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_IMR_TDC_FIFO2_OFFSET 1
`define TDC_EIC_EIC_IMR_TDC_FIFO2 32'h00000002
`define TDC_EIC_EIC_IMR_TDC_FIFO3_OFFSET 2
`define TDC_EIC_EIC_IMR_TDC_FIFO3 32'h00000004
`define TDC_EIC_EIC_IMR_TDC_FIFO4_OFFSET 3
`define TDC_EIC_EIC_IMR_TDC_FIFO4 32'h00000008
`define TDC_EIC_EIC_IMR_TDC_FIFO5_OFFSET 4
`define TDC_EIC_EIC_IMR_TDC_FIFO5 32'h00000010
`define TDC_EIC_EIC_IMR_TDC_DMA1_OFFSET 5
`define TDC_EIC_EIC_IMR_TDC_DMA1 32'h00000020
`define TDC_EIC_EIC_IMR_TDC_DMA2_OFFSET 6
`define TDC_EIC_EIC_IMR_TDC_DMA2 32'h00000040
`define TDC_EIC_EIC_IMR_TDC_DMA3_OFFSET 7
`define TDC_EIC_EIC_IMR_TDC_DMA3 32'h00000080
`define TDC_EIC_EIC_IMR_TDC_DMA4_OFFSET 8
`define TDC_EIC_EIC_IMR_TDC_DMA4 32'h00000100
`define TDC_EIC_EIC_IMR_TDC_DMA5_OFFSET 9
`define TDC_EIC_EIC_IMR_TDC_DMA5 32'h00000200
`define ADDR_TDC_EIC_EIC_ISR 6'h2c
`define TDC_EIC_EIC_ISR_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_ISR_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_ISR_TDC_FIFO2_OFFSET 1
`define TDC_EIC_EIC_ISR_TDC_FIFO2 32'h00000002
`define TDC_EIC_EIC_ISR_TDC_FIFO3_OFFSET 2
`define TDC_EIC_EIC_ISR_TDC_FIFO3 32'h00000004
`define TDC_EIC_EIC_ISR_TDC_FIFO4_OFFSET 3
`define TDC_EIC_EIC_ISR_TDC_FIFO4 32'h00000008
`define TDC_EIC_EIC_ISR_TDC_FIFO5_OFFSET 4
`define TDC_EIC_EIC_ISR_TDC_FIFO5 32'h00000010
`define TDC_EIC_EIC_ISR_TDC_DMA1_OFFSET 5
`define TDC_EIC_EIC_ISR_TDC_DMA1 32'h00000020
`define TDC_EIC_EIC_ISR_TDC_DMA2_OFFSET 6
`define TDC_EIC_EIC_ISR_TDC_DMA2 32'h00000040
`define TDC_EIC_EIC_ISR_TDC_DMA3_OFFSET 7
`define TDC_EIC_EIC_ISR_TDC_DMA3 32'h00000080
`define TDC_EIC_EIC_ISR_TDC_DMA4_OFFSET 8
`define TDC_EIC_EIC_ISR_TDC_DMA4 32'h00000100
`define TDC_EIC_EIC_ISR_TDC_DMA5_OFFSET 9
`define TDC_EIC_EIC_ISR_TDC_DMA5 32'h00000200
hdl/testbench/spec/buildinfo_pkg.vhd
View file @
3fdaa92b
...
...
@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant
buildinfo
:
string
:
=
"buildinfo:1"
&
LF
&
"module:main"
&
LF
&
"commit:
ca5ace53d7d35580770a3b79359c4a80fdd9775d
"
&
LF
&
"commit:
ac0bebbb3c3f294441ec6282b18a38b27bd8d61b
"
&
LF
&
"syntool:modelsim"
&
LF
&
"syndate:20
19-11-12, 18:04 CE
T"
&
LF
&
"syndate:20
20-04-22, 22:57 CES
T"
&
LF
&
"synauth:Evangelia Gousiou"
&
LF
;
end
buildinfo_pkg
;
hdl/testbench/spec/main.sv
View file @
3fdaa92b
...
...
@@ -2,13 +2,28 @@ import wishbone_pkg::*;
import
tdc_core_pkg
::*;
`include
"simdrv_defs.svh"
`include
"timestamp_fifo_regs.vh"
`include
"tdc_eic_wb_regs.vh"
`include
"tdc_core_csr_wb.vh"
`include
"vic_wb.vh"
`include
"gn4124_bfm.svh"
`include
"simdrv_defs.svh"
`include
"if_wb_master.svh"
`include
"vhd_wishbone_master.svh"
`include
"acam_model.svh"
`include
"softpll_regs_ng.vh"
`include
"gn4124_bfm.svh"
`include
"acam_model.svh"
`define
DMA_BASE
'
h00c0
`define
VIC_BASE
'
h0100
`define
TDC_CORE_BASE
'
h20000
`define
TDC_CORE_CFG_BASE
'
h2000
`define
FIFO1_BASE
'
h5000
`define
FIFO1_BASE
'
h5000
`define
TDC_EIC_BASE
'
h3000
`define
TDC_DMA_BASE
'
h6000
typedef
struct
{
uint32_t
tai
;
...
...
@@ -36,13 +51,14 @@ class FmcTdcDriver;
// writel
task
automatic
writel
(
uint32_t
addr
,
uint32_t
value
)
;
m_acc
.
write
(
addr
+
m_base
,
value
)
;
//$display("[Info] writel %x: %x", addr+m_base, value);
endtask
// readl
task
automatic
readl
(
uint32_t
addr
,
ref
uint32_t
value
)
;
automatic
uint64_t
rv
;
m_acc
.
read
(
addr
+
m_base
,
rv
)
;
$
display
(
"[Info] readl %x: %x"
,
addr
+
m_base
,
rv
)
;
//
$display("[Info] readl %x: %x", addr+m_base, rv);
value
=
rv
;
endtask
...
...
@@ -55,26 +71,31 @@ class FmcTdcDriver;
readl
(
'h0
,
d
)
;
if
(
d
!=
'h5344422d
)
begin
$
error
(
"[Error!] Can't read the SDB signature."
)
;
$
error
(
"[Error!] Can't read the SDB signature, reading: %x."
,
d
)
;
$
stop
;
end
readl
(
'h1000
,
d
)
;
readl
(
'h1004
,
d
)
;
readl
(
'h1008
,
d
)
;
readl
(
'h100C
,
d
)
;
if
(
d
==
'h5344422d
)
begin
$
display
(
"[Info] Found the SDB signature: %x"
,
d
)
;
end
// Configure the EIC for an interrupt on FIFO
writel
(
`TDC_EIC_BASE
+
`ADDR_TDC_EIC_EIC_IER
,
'h1F
)
;
writel
(
'h20a0
,
1234
)
;
// set UTC
// Configure the VIC
writel
(
`VIC_BASE
+
`ADDR_VIC_IER
,
'h7f
)
;
writel
(
`VIC_BASE
+
`ADDR_VIC_CTL
,
'h1
)
;
// Configure the TDC
$
display
(
"[Info] Setting up TDC core.."
)
;
writel
(
'h20a0
,
1234
)
;
// set UTC
writel
(
'h20fc
,
1
<<
9
)
;
// load UTC
writel
(
'h3004
,
'h1f
)
;
// enable EIC irqs for all FIFO channels
writel
(
'h2084
,
'h1f0000
)
;
// enable all ACAM inputs
writel
(
'h2090
,
2
)
;
// FIFO threshold = 2 ts
writel
(
'h2094
,
2
)
;
// FIFO threshold = 2 ms
writel
(
'h20fc
,
(
1
<<
0
))
;
// start acquisition
writel
(
'h20bc
,
((
-
1
)
<<
1
))
;
writel
(
`ADDR_TDC_CORE_CSR_UTC
+
`TDC_CORE_CFG_BASE
,
1234
)
;
// set UTC
writel
(
`ADDR_TDC_CORE_CSR_CTRL
+
`TDC_CORE_CFG_BASE
,
1
<<
9
)
;
// load UTC
writel
(
`ADDR_TDC_CORE_CSR_ENABLE
+
`TDC_CORE_CFG_BASE
,
'h1f0000
)
;
// enable all ACAM inputs
writel
(
`ADDR_TDC_CORE_CSR_IRQ_TSTAMP_THRESH
+
`TDC_CORE_CFG_BASE
,
2
)
;
// FIFO threshold = 2 ts
writel
(
`ADDR_TDC_CORE_CSR_IRQ_TIME_THRESH
+
`TDC_CORE_CFG_BASE
,
2
)
;
// FIFO threshold = 2 ms
writel
(
`ADDR_TDC_CORE_CSR_CTRL
+
`TDC_CORE_CFG_BASE
,
(
1
<<
0
))
;
// start acquisition
writel
(
'h20bc
,
((
-
1
)
<<
1
))
;
// test?
$
display
(
"[Info] TDC acquisition started"
)
;
...
...
@@ -84,21 +105,20 @@ class FmcTdcDriver;
task
automatic
update
()
;
automatic
uint32_t
csr
,
t
[
4
]
;
for
(
int
i
=
0
;
i
<
5
;
i
++
)
for
(
int
i
=
0
;
i
<
1
;
i
++
)
// only ch1 for now --
(int i = 0; i < 5; i++)
begin
automatic
uint32_t
base
=
'h5000
+
i
*
'h100
;
automatic
fmc_tdc_timestamp_t
ts
;
automatic
uint32_t
FIFObase
=
`FIFO1_BASE
+
i
*
'h100
;
automatic
fmc_tdc_timestamp_t
ts
,
ts1
,
ts2
;
readl
(
base
+
`ADDR_TSF_FIFO_CSR
,
csr
)
;
$
display
(
"csr %x"
,
csr
)
;
readl
(
FIFObase
+
`ADDR_TSF_FIFO_CSR
,
csr
)
;
if
(
!
(
csr
&
`TSF_FIFO_CSR_EMPTY
)
)
//$display("FIFO has values");
begin
readl
(
base
+
`ADDR_TSF_FIFO_R0
,
t
[
0
])
;
readl
(
base
+
`ADDR_TSF_FIFO_R1
,
t
[
1
])
;
readl
(
base
+
`ADDR_TSF_FIFO_R2
,
t
[
2
])
;
readl
(
base
+
`ADDR_TSF_FIFO_R3
,
t
[
3
])
;
readl
(
FIFO
base
+
`ADDR_TSF_FIFO_R0
,
t
[
0
])
;
readl
(
FIFO
base
+
`ADDR_TSF_FIFO_R1
,
t
[
1
])
;
readl
(
FIFO
base
+
`ADDR_TSF_FIFO_R2
,
t
[
2
])
;
readl
(
FIFO
base
+
`ADDR_TSF_FIFO_R3
,
t
[
3
])
;
ts
.
tai
=
t
[
0
]
;
ts
.
coarse
=
t
[
1
]
;
...
...
@@ -106,11 +126,20 @@ class FmcTdcDriver;
ts
.
slope
=
t
[
3
]
&
'h8
?
1
:
0
;
ts
.
seq
=
t
[
3
]
>>
4
;
ts
.
channel
=
i
;
m_queues
[
i
]
.
push_back
(
ts
)
;
end
end
// for (int i = 0; i < 5; i++)
endtask
endtask
// update_fifo
function
int
poll
()
;
$
display
(
"[Info] m_queues[0].size: %d"
,
m_queues
[
0
]
.
size
())
;
return
(
m_queues
[
0
]
.
size
()
>
2
)
;
endfunction
// poll
function
fmc_tdc_timestamp_t
get
()
;
return
m_queues
[
0
]
.
pop_front
()
;
endfunction
// get
endclass
// FmcTdcDriver
...
...
@@ -152,7 +181,7 @@ module main;
// ACAM model instantiation
tdc_gpx_model
#(
.
g_verbose
(
1
)
)
#(
.
g_verbose
(
0
)
)
ACAM
(
.
PuResN
(
1'b1
)
,
...
...
@@ -185,10 +214,7 @@ module main;
)
;
// GN4124 model instantiation
IGN4124PCIMaster
Host
(
)
;
IGN4124PCIMaster
Host
()
;
// TDC core instantiation
wr_spec_tdc
...
...
@@ -236,21 +262,16 @@ module main;
initial
begin
CBusAccessor
acc
;
FmcTdcDriver
drv
;
const
uint64_t
tdc1_base
=
'h20000
;
uint64_t
d
;
acc
=
Host
.
get_accessor
()
;
#
10u
s
;
// reset
//$display("Un-reset FMCs...");
//acc.write('h02000c, 'h3);
// test read
acc
.
read
(
'h2208c
,
d
)
;
// device instantiation
drv
=
new
(
acc
,
'h20000
,
0
)
;
drv
=
new
(
acc
,
`TDC_CORE_BASE
,
0
)
;
drv
.
init
()
;
$
display
(
"[Info] Start operation"
)
;
...
...
@@ -258,10 +279,27 @@ module main;
fork
forever
begin
drv
.
update
()
;
#
10u
s
;
if
(
drv
.
poll
())
begin
fmc_tdc_timestamp_t
ts1
,
ts2
;
uint64_t
timestmp1
,
timestmp2
,
diff
;
ts1
=
drv
.
get
()
;
timestmp1
=
ts1
.
tai
*
1e12
+
ts1
.
coarse
*
8e3
+
ts1
.
frac
*
81.03
;
$
display
(
"[Info] ts%d [%d:%d:%d src %d, slp: %d]: %d ps"
,
ts1
.
seq
,
ts1
.
tai
,
ts1
.
coarse
,
ts1
.
frac
,
ts1
.
channel
,
ts1
.
slope
,
timestmp1
)
;
ts2
=
drv
.
get
()
;
timestmp2
=
ts2
.
tai
*
1e12
+
ts2
.
coarse
*
8e3
+
ts2
.
frac
*
81.03
;
$
display
(
"[Info] ts%d [%d:%d:%d src %d, slp: %d]: %d ps"
,
ts2
.
seq
,
ts2
.
tai
,
ts2
.
coarse
,
ts2
.
frac
,
ts2
.
channel
,
ts2
.
slope
,
timestmp2
)
;
if
(
timestmp1
>
timestmp2
)
begin
diff
=
timestmp1
-
timestmp2
;
$
display
(
"[Info] Period: ts%d - ts%d: %d"
,
ts1
.
seq
,
ts2
.
seq
,
diff
)
;
end
else
begin
diff
=
timestmp2
-
timestmp1
;
$
display
(
"[Info] Period: ts%d - ts%d: %d"
,
ts2
.
seq
,
ts1
.
seq
,
diff
)
;
end
end
end
forever
begin
// generate pulses to TDC channel 1
#
700
ns
;
tdc_stop
[
1
]
<=
1
;
#
300
ns
;
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment