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FMC TDC 1ns 5cha - Gateware
Commit 1e1a8a0a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Initial version of DMA SPEC gateware, briefly validated in HW

parent 0f830c2a
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.gitmodules
View file @ 1e1a8a0a
......@@ -10,3 +10,6 @@
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
ddr3-sp6-core @ 50317193
Subproject commit 503171933f184ae878836f28e67a78a7c81b4325
hdl/rtl/Manifest.py
View file @ 1e1a8a0a
files = [
"tdc_core_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd"
"tdc_core_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd",
"timestamp_convert_filter.vhd",
"tdc_dma_channel.vhd",
"tdc_dma_engine.vhd",
"tdc_buffer_control_regs.vhd",
"tdc_buffer_control_regs_wbgen2_pkg.vhd"
];
hdl/rtl/build_wb.sh 0 → 100755
View file @ 1e1a8a0a
#!/bin/bash
wbgen2 -V timestamp_fifo_wb.vhd -H record_full -p timestamp_fifo_wbgen2_pkg.vhd -K timestamp_fifo_regs.vh -s defines -C timestamp_fifo_regs.h -D wbgen/timestamp_fifo_wb.html wbgen/timestamp_fifo_wb.wb
wbgen2 -V tdc_buffer_control_regs.vhd -H record_full -p tdc_buffer_control_regs_wbgen2_pkg.vhd -K tdc_buffer_control_regs.vh -s defines -C tdc_buffer_control_regs.h wbgen/tdc_buffer_control_regs.wb
#don't do this, latest wbgen is buggy
#wbgen2 -V tdc_eic.vhd -s defines -C tdc_eic.h -D wbgen/tdc_eic.html wbgen/tdc_eic.wb
hdl/rtl/data_formatting.vhd
View file @ 1e1a8a0a
......@@ -101,7 +101,7 @@ entity data_formatting is
-- OUTPUTS
timestamp_o : out std_logic_vector(127 downto 0);
timestamp_o : out t_raw_acam_timestamp;
timestamp_valid_o : out std_logic
);
......@@ -335,11 +335,21 @@ begin
full_timestamp(127 downto 96) <= metadata;
process(clk_i)
begin
if rising_edge(clk_i) then
timestamp_o <= full_timestamp;
timestamp_valid_o <= timestamp_valid_int;
if(timestamp_valid_int = '1') then
timestamp_o.slope <= acam_slope;
timestamp_o.channel <= acam_channel;
timestamp_o.n_bins <= fine_time(16 downto 0);
timestamp_o.coarse <= coarse_time;
timestamp_o.tai <= utc;
timestamp_valid_o <= '1';
else
timestamp_valid_o <= '0';
end if;
end if;
end process;
......
hdl/rtl/fmc_tdc_core.vhd
View file @ 1e1a8a0a
......@@ -17,12 +17,6 @@
-- |
-- Figure 1 shows the architecture of this core. |
-- |
-- Each timestamp is a 128-bit word with the following structure: |
-- [31:0] Fine time | each bit represents 81.03 ps |
-- [63:32] Coarse time within the current second | each bit represents 8 ns |
-- [95:64] Local UTC time | each bit represents 1 s |
-- [127:96] Metadata | rising/falling tstamp, Channel |
-- |
-- As the structure indicates, each timestamp is referred to a UTC second; the coarse|
-- and fine time indicate with 81.03 ps resolution the amount of time passed after |
-- the last UTC second. |
......@@ -163,10 +157,10 @@ entity fmc_tdc_core is
port
(
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
clk_tdc_i : in std_logic; -- 125 MHz reference from the PLL
rst_tdc_i : in std_logic; -- global reset, synched to clk_tdc_i
rst_tdc_n_i : in std_logic; -- global reset, synched to clk_tdc_i
acam_refclk_r_edge_p_i : in std_logic; -- rising edge on 31.25MHz ACAM reference clock
send_dac_word_p_o : out std_logic; -- command from GN4124/VME to reconfigure the TDC mezz DAC with dac_word_o
......@@ -200,12 +194,6 @@ entity fmc_tdc_core is
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 termination
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 termination
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 termination
-- TDC input signals, also arriving to the FPGA; not used currently
tdc_in_fpga_1_i : in std_logic; -- TDC input Ch.1, not used
tdc_in_fpga_2_i : in std_logic; -- TDC input Ch.2, not used
tdc_in_fpga_3_i : in std_logic; -- TDC input Ch.3, not used
tdc_in_fpga_4_i : in std_logic; -- TDC input Ch.4, not used
tdc_in_fpga_5_i : in std_logic; -- TDC input Ch.5, not used
-- White Rabbit control and status registers
......@@ -221,8 +209,9 @@ entity fmc_tdc_core is
cfg_slave_i : in t_wishbone_slave_in;
cfg_slave_o : out t_wishbone_slave_out;
timestamp_o : out std_logic_vector(127 downto 0);
timestamp_stb_o : out std_logic;
timestamp_o : out t_tdc_timestamp_array(4 downto 0);
timestamp_valid_o : out std_logic_vector(4 downto 0);
timestamp_ready_i : in std_logic_vector(4 downto 0);
channel_enable_o : out std_logic_vector(4 downto 0);
irq_threshold_o : out std_logic_vector(9 downto 0);
......@@ -268,34 +257,39 @@ architecture rtl of fmc_tdc_core is
-- LEDs
signal acam_channel : std_logic_vector(5 downto 0);
signal tdc_in_fpga_1, tdc_in_fpga_2, tdc_in_fpga_3 : std_logic_vector(1 downto 0);
signal tdc_in_fpga_4, tdc_in_fpga_5 : std_logic_vector(1 downto 0);
signal acam_tstamp_channel : std_logic_vector(2 downto 0);
signal rst_sys : std_logic;
signal timestamp_valid : std_logic;
signal timestamp : std_logic_vector(127 downto 0);
signal raw_timestamp_valid : std_logic;
signal raw_timestamp : t_raw_acam_timestamp;
signal final_timestamp_valid : std_logic_vector(4 downto 0);
signal final_timestamp_ready : std_logic_vector(4 downto 0);
signal final_timestamp : t_tdc_timestamp_array(4 downto 0);
signal channel_enable_int : std_logic_vector(4 downto 0);
signal rst_sys, rst_tdc : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
rst_sys <= not rst_n_sys_i;
rst_sys <= not rst_sys_n_i;
rst_tdc <= not rst_tdc_n_i;
---------------------------------------------------------------------------------------------------
-- TDC REGISTERS CONTROLLER --
---------------------------------------------------------------------------------------------------
reg_control_block : reg_ctrl
reg_control_block : entity work.reg_ctrl
generic map
(g_span => g_span,
g_width => g_width)
port map
(clk_tdc_i => clk_tdc_i,
rst_tdc_i => rst_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_n_sys_i,
rst_sys_n_i => rst_sys_n_i,
slave_i => cfg_slave_i,
......@@ -348,7 +342,7 @@ begin
term_enable_regs : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i = '1' then
if rst_tdc_n_i = '0' then
enable_inputs_o <= '0';
term_en_5_o <= '0';
term_en_4_o <= '0';
......@@ -379,7 +373,7 @@ begin
clk_period_i => clk_period,
load_utc_p_i => load_utc,
pulse_delay_i => pulse_delay,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
starting_utc_i => starting_utc,
local_utc_o => local_utc,
local_utc_p_o => local_utc_p);
......@@ -400,7 +394,7 @@ begin
activate_acq_p_i => activate_acq_p,
state_active_p_i => state_active_p,
deactivate_acq_p_i => deactivate_acq_p,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
acam_errflag_f_edge_p_o => acam_errflag_f_edge_p,
acam_errflag_r_edge_p_o => acam_errflag_r_edge_p,
acam_intflag_f_edge_p_o => acam_intflag_f_edge_p);
......@@ -426,7 +420,7 @@ begin
ef2_o => acam_ef2,
ef2_meta_o => acam_ef2_meta,
clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
adr_i => acm_adr,
cyc_i => acm_cyc,
dat_i => acm_dat_w,
......@@ -446,7 +440,7 @@ begin
(acam_intflag_f_edge_p_i => acam_intflag_f_edge_p,
clk_i => clk_tdc_i,
utc_p_i => utc_p,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
current_retrig_nb_o => current_retrig_nb, -- for debug
roll_over_incr_recent_o => roll_over_incr_recent,
clk_i_cycles_offset_o => clk_i_cycles_offset,
......@@ -469,7 +463,7 @@ begin
acam_stb_o => acm_stb,
acam_we_o => acm_we,
clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
acam_ef1_i => acam_ef1,
acam_ef1_meta_i => acam_ef1_meta,
acam_ef2_i => acam_ef2,
......@@ -499,10 +493,10 @@ begin
---------------------------------------------------------------------------------------------------
-- DATA FORMATTING --
---------------------------------------------------------------------------------------------------
data_formatting_block : data_formatting
data_formatting_block : entity work.data_formatting
port map
(clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
acam_tstamp1_i => acam_tstamp1,
acam_tstamp1_ok_p_i => acam_tstamp1_ok_p,
acam_tstamp2_i => acam_tstamp2,
......@@ -513,8 +507,24 @@ begin
retrig_nb_offset_i => retrig_nb_offset,
utc_p_i => utc_p,
utc_i => utc,
timestamp_o => timestamp,
timestamp_valid_o => timestamp_valid
timestamp_o => raw_timestamp,
timestamp_valid_o => raw_timestamp_valid
);
U_FilterAndConvert : entity work.timestamp_convert_filter
port map (
clk_tdc_i => clk_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
enable_i => channel_enable_int,
ts_i => raw_timestamp,
ts_valid_i => raw_timestamp_valid,
ts_o => final_timestamp,
ts_valid_o => final_timestamp_valid,
ts_ready_i => final_timestamp_ready
);
......@@ -524,8 +534,9 @@ begin
utc <= wrabbit_tai_i when wrabbit_synched_i = '1' else local_utc;
utc_p <= wrabbit_tai_p_i when wrabbit_synched_i = '1' else local_utc_p;
timestamp_stb_o <= timestamp_valid;
timestamp_o <= timestamp;
timestamp_valid_o <= final_timestamp_valid;
final_timestamp_ready <= timestamp_ready_i;
timestamp_o <= final_timestamp;
---------------------------------------------------------------------------------------------------
-- TDC LEDs --
......@@ -536,11 +547,11 @@ begin
g_simulation => g_simulation)
port map
(clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
rst_i => rst_tdc,
utc_p_i => local_utc_p,
acam_inputs_en_i => acam_inputs_en,
acam_channel_i => acam_channel,
tstamp_wr_p_i => timestamp_valid,
tstamp_wr_p_i => final_timestamp_valid(0),
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
......@@ -555,7 +566,8 @@ begin
---------------------------------------------------------------------------------------------------
start_dis_o <= '0';
channel_enable_o <= acam_inputs_en(20 downto 16);
channel_enable_int <= acam_inputs_en(20 downto 16);
channel_enable_o <= channel_enable_int;
end rtl;
----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 1e1a8a0a
......@@ -109,7 +109,8 @@ entity fmc_tdc_mezzanine is
(g_with_wrabbit_core : boolean := false;
g_span : integer := 32;
g_width : integer := 32;
g_simulation : boolean := false);
g_simulation : boolean := false;
g_use_dma_readout : boolean := true );
port
-- TDC core
(
......@@ -120,7 +121,7 @@ entity fmc_tdc_mezzanine is
-- TDC 125 MHz reference & Reset (FMC)
clk_tdc_i : in std_logic; -- 125 MHz clock
rst_tdc_i : in std_logic; -- reset for 125 MHz logic
rst_tdc_n_i : in std_logic; -- reset for 125 MHz logic
acam_refclk_r_edge_p_i : in std_logic;
send_dac_word_p_o : out std_logic;
......@@ -153,12 +154,6 @@ entity fmc_tdc_mezzanine is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- Input pulses arriving also to the FPGA, currently not treated
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
-- White Rabbit core
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic;
......@@ -176,6 +171,9 @@ entity fmc_tdc_mezzanine is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in;
wb_irq_o : out std_logic;
-- I2C EEPROM interface
......@@ -198,37 +196,17 @@ end fmc_tdc_mezzanine;
--=================================================================================================
architecture rtl of fmc_tdc_mezzanine is
component timestamp_fifo is
generic (
g_channel : integer);
port (
clk_sys_i : in std_logic;
clk_tdc_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_tdc_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_o : out std_logic;
enable_i : in std_logic;
tick_i : in std_logic;
irq_threshold_i : in std_logic_vector(9 downto 0);
irq_timeout_i : in std_logic_vector(9 downto 0);
timestamp_i : in std_logic_vector(127 downto 0);
timestamp_valid_i : in std_logic);
end component timestamp_fifo;
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 9;
constant c_WB_SLAVE_TDC_ONEWIRE : integer := 0; -- TDC mezzanine board UnidueID&Thermometer 1-wire
constant c_WB_SLAVE_TDC_CORE_CONFIG : integer := 1; -- TDC core configuration registers
constant c_WB_SLAVE_TDC_EIC : integer := 2; -- TDC interrupts
constant c_WB_SLAVE_TDC_I2C : integer := 3; -- TDC mezzanine board system EEPROM I2C
constant c_WB_SLAVE_TDC_FIFO0 : integer := 4; -- Access to TDC core FIFO for timestamps retrieval
constant c_WB_SLAVE_TDC_FIFO0_DMA : integer := 4; -- Access to TDC core FIFO for timestamps retrieval
-- Slave port on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
......@@ -239,8 +217,10 @@ architecture rtl of fmc_tdc_mezzanine is
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_NUM_WB_MASTERS_FIFO : integer := 9;
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
constant c_INTERCONNECT_LAYOUT_FIFO : t_sdb_record_array(c_NUM_WB_MASTERS_FIFO-1 downto 0) :=
(0 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00002000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00003000"),
......@@ -252,6 +232,37 @@ architecture rtl of fmc_tdc_mezzanine is
8 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005400")
);
constant c_NUM_WB_MASTERS_DMA : integer := 5;
-- WISHBONE crossbar layout
constant c_INTERCONNECT_LAYOUT_DMA : t_sdb_record_array(c_NUM_WB_MASTERS_DMA-1 downto 0) :=
(0 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00002000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00003000"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00004000"),
4 => f_sdb_embed_device(c_TDC_DMA_SDB_DEVICE, x"00005000")
);
function f_num_interconnect_num_wb_masters return integer is
begin
if g_use_dma_readout then
return c_NUM_WB_MASTERS_DMA;
else
return c_NUM_WB_MASTERS_FIFO;
end if;
end f_num_interconnect_num_wb_masters;
function f_interconnect_layout return t_sdb_record_array is
begin
if g_use_dma_readout then
return c_INTERCONNECT_LAYOUT_DMA;
else
return c_INTERCONNECT_LAYOUT_FIFO;
end if;
end f_interconnect_layout;
---------------------------------------------------------------------------------------------------
-- Signals --
......@@ -259,8 +270,8 @@ architecture rtl of fmc_tdc_mezzanine is
-- resets
signal general_rst_n, rst_ref_0_n : std_logic;
-- Wishbone buse(s) from crossbar master port(s)
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(f_num_interconnect_num_wb_masters-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (f_num_interconnect_num_wb_masters-1 downto 0);
-- WISHBONE addresses
signal tdc_core_wb_adr : std_logic_vector(31 downto 0);
......@@ -280,13 +291,14 @@ architecture rtl of fmc_tdc_mezzanine is
signal irq_channel : std_logic_vector(4 downto 0);
signal timestamp : std_logic_vector(127 downto 0);
signal timestamp_stb : std_logic;
signal timestamp : t_tdc_timestamp_array(4 downto 0);
signal timestamp_valid, timestamp_ready, timestamp_stb : std_logic_vector(4 downto 0);
signal channel_enable : std_logic_vector(4 downto 0);
signal irq_threshold, irq_timeout : std_logic_vector(9 downto 0);
signal tick_1ms : std_logic;
signal counter_1ms : unsigned(17 downto 0);
function f_wb_shift_address_word (w : t_wishbone_master_out) return t_wishbone_master_out is
variable r : t_wishbone_master_out;
begin
......@@ -304,15 +316,13 @@ architecture rtl of fmc_tdc_mezzanine is
--=================================================================================================
begin
rst_ref_0_n <= not(rst_tdc_i);
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_num_slaves => f_num_interconnect_num_wb_masters,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_layout => f_interconnect_layout,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_sys_i,
......@@ -326,7 +336,7 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC CORE --
---------------------------------------------------------------------------------------------------
cmp_tdc_core : fmc_tdc_core
cmp_tdc_core : entity work.fmc_tdc_core
generic map
(g_span => g_span,
g_width => g_width,
......@@ -334,9 +344,10 @@ begin
port map
( -- clks, rst
clk_tdc_i => clk_tdc_i,
rst_tdc_i => rst_tdc_i,
rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_sys_n_i,
rst_sys_n_i => rst_sys_n_i,
acam_refclk_r_edge_p_i => acam_refclk_r_edge_p_i,
-- DAC configuration
send_dac_word_p_o => send_dac_word_p_o,
......@@ -362,12 +373,6 @@ begin
term_en_3_o => term_en_3_o,
term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o,
-- Input channels to FPGA (not used currently)
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
-- TDC board LEDs
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
......@@ -388,24 +393,29 @@ begin
cfg_slave_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG),
timestamp_o => timestamp,
timestamp_stb_o => timestamp_stb,
timestamp_valid_o => timestamp_valid,
timestamp_ready_i => timestamp_ready,
irq_threshold_o => irq_threshold,
irq_timeout_o => irq_timeout,
channel_enable_o => channel_enable
);
gen_without_dma_readout : if not g_use_dma_readout generate
gen_fifos : for i in 0 to 4 generate
U_TheFifo : timestamp_fifo
U_TheFifo : entity work.timestamp_fifo
generic map (
g_channel => i)
port map (
clk_sys_i => clk_sys_i,
clk_tdc_i => clk_tdc_i,
rst_n_sys_i => rst_sys_n_i,
rst_tdc_i => rst_tdc_i,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_FIFO0 + i),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i),
rst_sys_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_FIFO0_DMA + i),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_FIFO0_DMA + i),
irq_o => irq_channel(i),
enable_i => channel_enable(i),
tick_i => tick_1ms,
......@@ -414,12 +424,37 @@ begin
timestamp_i => timestamp,
timestamp_valid_i => timestamp_stb);
timestamp_stb(i) <= timestamp_valid(i);
timestamp_ready(i) <= '1';
end generate gen_fifos;
end generate gen_without_dma_readout;
gen_with_dma_readout : if g_use_dma_readout generate
U_DMA_Engine : entity work.tdc_dma_engine
generic map (
g_CLOCK_FREQ => 62500000)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
ts_i => timestamp,
ts_valid_i => timestamp_valid,
ts_ready_o => timestamp_ready,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_FIFO0_DMA),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_FIFO0_DMA),
irq_o => irq_channel ,
dma_wb_o => dma_wb_o,
dma_wb_i => dma_wb_i);
end generate gen_with_dma_readout;
p_gen_1ms_tick : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
if rst_tdc_n_i = '0' then
tick_1ms <= '0';
counter_1ms <= (others => '0');
else
......@@ -445,7 +480,7 @@ begin
(clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_sys_n_i,
clk_ref_i => clk_tdc_i,
rst_n_ref_i => rst_ref_0_n,
rst_n_ref_i => rst_tdc_n_i,
wrabbit_dac_value_i => wrabbit_dac_value_i,
wrabbit_dac_wr_p_i => wrabbit_dac_wr_p_i,
wrabbit_link_up_i => wrabbit_link_up_i,
......@@ -461,7 +496,7 @@ begin
wrabbit_one_hz_pulse : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_ref_0_n = '0' then
if rst_tdc_n_i = '0' then
wrabbit_utc_p <= '0';
else
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
......@@ -510,7 +545,7 @@ begin
-- 0 -> number of accumulated timestamps reached threshold
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
cmp_tdc_eic : tdc_eic
cmp_tdc_eic : entity work.tdc_eic
port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ 1e1a8a0a
......@@ -131,7 +131,9 @@ entity fmc_tdc_wrapper is
-- reduces some timeouts to speed up simulation
g_simulation : boolean := false;
-- implement direct TDC timestamp readout FIFO, used in the WR Node projects
g_with_direct_readout : boolean := false
g_with_direct_readout : boolean := false;
g_use_dma_readout : boolean := false
);
port
......@@ -184,12 +186,6 @@ entity fmc_tdc_wrapper is
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Input Logic on TDC mezzanine (not used currently)
tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-- I2C EEPROM interface on TDC mezzanine
mezz_scl_o : out std_logic;
......@@ -220,9 +216,12 @@ entity fmc_tdc_wrapper is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
direct_slave_i : in t_wishbone_slave_in;
direct_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
direct_slave_o : out t_wishbone_slave_out;
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in := cc_dummy_master_in;
irq_o : out std_logic;
-- local PLL clock output (for WR PTP Core clock disciplining)
......@@ -366,23 +365,27 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC BOARD --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezz : fmc_tdc_mezzanine
cmp_tdc_mezz : entity work.fmc_tdc_mezzanine
generic map
(g_span => 32,
g_width => 32,
g_simulation => g_simulation)
g_simulation => g_simulation,
g_use_dma_readout => g_use_dma_readout)
port map
-- 62M5 clk and reset
(clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
-- 125M clk and reset
clk_tdc_i => clk_125m_mezz,
rst_tdc_i => rst_125m_mezz,
rst_tdc_n_i => rst_125m_mezz_n,
-- Wishbone
slave_i => cnx_master_out(c_slave_regs),
slave_o => cnx_master_in(c_slave_regs),
dma_wb_i => dma_wb_i,
dma_wb_o => dma_wb_o,
-- Interrupt line from EIC
wb_irq_o => irq_o,
......@@ -418,12 +421,6 @@ begin
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- Input channels to FPGA (not used)
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
-- WISHBONE interface with the GN4124 core
-- White Rabbit
......
hdl/rtl/reg_ctrl.vhd
View file @ 1e1a8a0a
......@@ -81,18 +81,20 @@ use work.wishbone_pkg.all;
entity reg_ctrl is
generic
(g_span : integer := 32;
g_width : integer := 32);
(
g_span : integer := 32;
g_width : integer := 32
);
port
(
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic; -- global reset, synched to clk_sys
rst_sys_n_i : in std_logic; -- global reset, synched to clk_sys
clk_tdc_i : in std_logic;
rst_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
slave_i: in t_wishbone_slave_in; -- WB interface (clk_sys domain)
slave_o: out t_wishbone_slave_out;
slave_i : in t_wishbone_slave_in; -- WB interface (clk_sys domain)
slave_o : out t_wishbone_slave_out;
-- Signals from the data_engine unit: configuration regs read back from the ACAM
acam_config_rdbk_i : in config_vector; -- array keeping values read back from ACAM regs 0-7, 11, 12, 14
......@@ -133,7 +135,7 @@ entity reg_ctrl is
-- Signal to the one_hz_gen unit
load_utc_p_o : out std_logic;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
irq_tstamp_threshold_o: out std_logic_vector(g_width-1 downto 0); -- threshold in number of timestamps
irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of timestamps
irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0); -- threshold in number of ms
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0); -- for debug only
......@@ -155,7 +157,7 @@ end reg_ctrl;
architecture rtl of reg_ctrl is
signal acam_config : config_vector;
signal reg_adr,reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal reg_adr, reg_adr_pipe0 : std_logic_vector(7 downto 0);
signal starting_utc, acam_inputs_en, start_phase : std_logic_vector(g_width-1 downto 0);
signal ctrl_reg, one_hz_phase, irq_tstamp_threshold : std_logic_vector(g_width-1 downto 0);
signal irq_time_threshold : std_logic_vector(g_width-1 downto 0);
......@@ -177,7 +179,6 @@ architecture rtl of reg_ctrl is
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
signal rst_n_tdc : std_logic;
......@@ -190,8 +191,6 @@ architecture rtl of reg_ctrl is
begin
rst_n_tdc <= not rst_tdc_i;
wb_out.stall <= '0';
wb_out.err <= '0';
wb_out.rty <= '0';
......@@ -199,11 +198,11 @@ begin
u_sync_tdc_reset : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
data_i => rst_n_tdc,
rst_n_i => rst_sys_n_i,
data_i => rst_tdc_n_i,
synced_o => cc_rst_n);
cc_rst_n_or_sys <= cc_rst_n and rst_n_sys_i;
cc_rst_n_or_sys <= cc_rst_n and rst_sys_n_i;
cmp_clks_crossing : xwb_clock_crossing
port map
......@@ -212,7 +211,7 @@ begin
slave_i => slave_i,
slave_o => slave_o,
master_clk_i => clk_tdc_i,
master_rst_n_i => rst_n_tdc,
master_rst_n_i => rst_tdc_n_i,
master_i => wb_out,
master_o => wb_in);
......@@ -228,12 +227,12 @@ begin
TDCconfig_ack_generator : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_n_tdc = '0' then
if rst_tdc_n_i = '0' then
wb_out.ack <= '0';
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
elsif(wb_in.cyc = '0') then
elsif(wb_in.cyc /= '1') then
ack_out_pipe1 <= '0';
ack_out_pipe0 <= '0';
cyc_in_progress <= '0';
......@@ -259,18 +258,18 @@ begin
ACAM_config_reg_reception : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i = '1' then
acam_config(0) <= (others =>'0');
acam_config(1) <= (others =>'0');
acam_config(2) <= (others =>'0');
acam_config(3) <= (others =>'0');
acam_config(4) <= (others =>'0');
acam_config(5) <= (others =>'0');
acam_config(6) <= (others =>'0');
acam_config(7) <= (others =>'0');
acam_config(8) <= (others =>'0');
acam_config(9) <= (others =>'0');
acam_config(10) <= (others =>'0');
if rst_tdc_n_i = '0' then
acam_config(0) <= (others => '0');
acam_config(1) <= (others => '0');
acam_config(2) <= (others => '0');
acam_config(3) <= (others => '0');
acam_config(4) <= (others => '0');
acam_config(5) <= (others => '0');
acam_config(6) <= (others => '0');
acam_config(7) <= (others => '0');
acam_config(8) <= (others => '0');
acam_config(9) <= (others => '0');
acam_config(10) <= (others => '0');
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then -- WISHBONE writes
......@@ -339,15 +338,15 @@ begin
-- o one_hz_phase : eva: think it s not used
-- o start_phase : eva: think it s not used
TDCcore_config_reg_reception: process (clk_tdc_i)
TDCcore_config_reg_reception : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i ='1' then
acam_inputs_en <= (others =>'0');
starting_utc <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
wrabbit_ctrl_reg <= (others =>'0');
if rst_tdc_n_i = '0' then
acam_inputs_en <= (others => '0');
starting_utc <= (others => '0');
start_phase <= (others => '0');
one_hz_phase <= (others => '0');
wrabbit_ctrl_reg <= (others => '0');
irq_tstamp_threshold <= x"00000001"; -- default 256 timestamps: full memory
irq_time_threshold <= x"00000001"; -- default 200 ms
dac_word <= c_DEFAULT_DAC_WORD; -- default DAC Vout = 1.65
......@@ -412,12 +411,12 @@ begin
TDCcore_ctrl_reg_reception : process (clk_tdc_i)
begin
if rising_edge (clk_tdc_i) then
if rst_tdc_i = '1' then
ctrl_reg <= (others =>'0');
if rst_tdc_n_i = '0' then
ctrl_reg <= (others => '0');
clear_ctrl_reg <= '0';
elsif clear_ctrl_reg = '1' then
ctrl_reg <= (others =>'0');
ctrl_reg <= (others => '0');
clear_ctrl_reg <= '0';
elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
......@@ -447,7 +446,7 @@ begin
-- Pulse_stretcher: Increases the width of the send_dac_word_p pulse so that it can be sampled
-- by the 20 MHz clock of the clks_rsts_manager that is communicating with the DAC.
Pulse_stretcher: incr_counter
Pulse_stretcher : incr_counter
generic map
(width => 3)
port map
......
hdl/rtl/tdc_buffer_control_regs.vhd 0 → 100644
View file @ 1e1a8a0a
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Buffer Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_buffer_control_regs.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_buffer_control_regs.wb
-- Created : Thu Jul 19 17:10:58 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_buffer_control_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.TDC_BUF_wbgen2_pkg.all;
entity tdc_buffer_control_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDC_BUF_in_registers;
regs_o : out t_TDC_BUF_out_registers
);
end tdc_buffer_control_wb;
architecture syn of tdc_buffer_control_wb is
signal tdc_buf_csr_enable_int : std_logic ;
signal tdc_buf_csr_irq_timeout_int : std_logic_vector(9 downto 0);
signal tdc_buf_csr_burst_size_int : std_logic_vector(9 downto 0);
signal tdc_buf_csr_switch_buffers_dly0 : std_logic ;
signal tdc_buf_csr_switch_buffers_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tdc_buf_csr_enable_int <= '0';
tdc_buf_csr_irq_timeout_int <= "0000000000";
tdc_buf_csr_burst_size_int <= "0000000000";
tdc_buf_csr_switch_buffers_int <= '0';
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tdc_buf_csr_switch_buffers_int <= '0';
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (slave_i.we = '1') then
tdc_buf_csr_enable_int <= wrdata_reg(0);
tdc_buf_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
tdc_buf_csr_burst_size_int <= wrdata_reg(20 downto 11);
tdc_buf_csr_switch_buffers_int <= wrdata_reg(21);
regs_o.tdc_buf_csr_done_load_o <= '1';
regs_o.tdc_buf_csr_overflow_load_o <= '1';
end if;
rddata_reg(0) <= tdc_buf_csr_enable_int;
rddata_reg(10 downto 1) <= tdc_buf_csr_irq_timeout_int;
rddata_reg(20 downto 11) <= tdc_buf_csr_burst_size_int;
rddata_reg(21) <= '0';
rddata_reg(22) <= regs_i.tdc_buf_csr_done_i;
rddata_reg(23) <= regs_i.tdc_buf_csr_overflow_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_size_size_load_o <= '1';
regs_o.tdc_buf_cur_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdc_buf_cur_size_size_i;
rddata_reg(30) <= regs_i.tdc_buf_cur_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_size_size_load_o <= '1';
regs_o.tdc_buf_next_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdc_buf_next_size_size_i;
rddata_reg(30) <= regs_i.tdc_buf_next_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Enable DMA
regs_o.tdc_buf_csr_enable_o <= tdc_buf_csr_enable_int;
-- IRQ Timeout (ms)
regs_o.tdc_buf_csr_irq_timeout_o <= tdc_buf_csr_irq_timeout_int;
-- Burst size (timestamps)
regs_o.tdc_buf_csr_burst_size_o <= tdc_buf_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_buf_csr_switch_buffers_dly0 <= '0';
regs_o.tdc_buf_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
tdc_buf_csr_switch_buffers_dly0 <= tdc_buf_csr_switch_buffers_int;
regs_o.tdc_buf_csr_switch_buffers_o <= tdc_buf_csr_switch_buffers_int and (not tdc_buf_csr_switch_buffers_dly0);
end if;
end process;
-- DMA complete
regs_o.tdc_buf_csr_done_o <= wrdata_reg(22);
-- DMA overflow
regs_o.tdc_buf_csr_overflow_o <= wrdata_reg(23);
-- Base address
regs_o.tdc_buf_cur_base_o <= wrdata_reg(31 downto 0);
-- Number of data samples in the buffer
-- Size (in transfers)
regs_o.tdc_buf_cur_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdc_buf_cur_size_valid_o <= wrdata_reg(30);
-- Base address
regs_o.tdc_buf_next_base_o <= wrdata_reg(31 downto 0);
-- Size (in transfers)
regs_o.tdc_buf_next_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdc_buf_next_size_valid_o <= wrdata_reg(30);
rwaddr_reg <= slave_i.adr(4 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
hdl/rtl/tdc_buffer_control_regs_wbgen2_pkg.vhd 0 → 100644
View file @ 1e1a8a0a
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Buffer Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_buffer_control_regs_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_buffer_control_regs.wb
-- Created : Thu Jul 19 17:10:58 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_buffer_control_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDC_BUF_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDC_BUF_in_registers is record
tdc_buf_csr_done_i : std_logic;
tdc_buf_csr_overflow_i : std_logic;
tdc_buf_cur_base_i : std_logic_vector(31 downto 0);
tdc_buf_cur_count_i : std_logic_vector(31 downto 0);
tdc_buf_cur_size_size_i : std_logic_vector(29 downto 0);
tdc_buf_cur_size_valid_i : std_logic;
tdc_buf_next_base_i : std_logic_vector(31 downto 0);
tdc_buf_next_size_size_i : std_logic_vector(29 downto 0);
tdc_buf_next_size_valid_i : std_logic;
end record;
constant c_TDC_BUF_in_registers_init_value: t_TDC_BUF_in_registers := (
tdc_buf_csr_done_i => '0',
tdc_buf_csr_overflow_i => '0',
tdc_buf_cur_base_i => (others => '0'),
tdc_buf_cur_count_i => (others => '0'),
tdc_buf_cur_size_size_i => (others => '0'),
tdc_buf_cur_size_valid_i => '0',
tdc_buf_next_base_i => (others => '0'),
tdc_buf_next_size_size_i => (others => '0'),
tdc_buf_next_size_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_TDC_BUF_out_registers is record
tdc_buf_csr_enable_o : std_logic;
tdc_buf_csr_irq_timeout_o : std_logic_vector(9 downto 0);
tdc_buf_csr_burst_size_o : std_logic_vector(9 downto 0);
tdc_buf_csr_switch_buffers_o : std_logic;
tdc_buf_csr_done_o : std_logic;
tdc_buf_csr_done_load_o : std_logic;
tdc_buf_csr_overflow_o : std_logic;
tdc_buf_csr_overflow_load_o : std_logic;
tdc_buf_cur_base_o : std_logic_vector(31 downto 0);
tdc_buf_cur_base_load_o : std_logic;
tdc_buf_cur_size_size_o : std_logic_vector(29 downto 0);
tdc_buf_cur_size_size_load_o : std_logic;
tdc_buf_cur_size_valid_o : std_logic;
tdc_buf_cur_size_valid_load_o : std_logic;
tdc_buf_next_base_o : std_logic_vector(31 downto 0);
tdc_buf_next_base_load_o : std_logic;
tdc_buf_next_size_size_o : std_logic_vector(29 downto 0);
tdc_buf_next_size_size_load_o : std_logic;
tdc_buf_next_size_valid_o : std_logic;
tdc_buf_next_size_valid_load_o : std_logic;
end record;
constant c_TDC_BUF_out_registers_init_value: t_TDC_BUF_out_registers := (
tdc_buf_csr_enable_o => '0',
tdc_buf_csr_irq_timeout_o => (others => '0'),
tdc_buf_csr_burst_size_o => (others => '0'),
tdc_buf_csr_switch_buffers_o => '0',
tdc_buf_csr_done_o => '0',
tdc_buf_csr_done_load_o => '0',
tdc_buf_csr_overflow_o => '0',
tdc_buf_csr_overflow_load_o => '0',
tdc_buf_cur_base_o => (others => '0'),
tdc_buf_cur_base_load_o => '0',
tdc_buf_cur_size_size_o => (others => '0'),
tdc_buf_cur_size_size_load_o => '0',
tdc_buf_cur_size_valid_o => '0',
tdc_buf_cur_size_valid_load_o => '0',
tdc_buf_next_base_o => (others => '0'),
tdc_buf_next_base_load_o => '0',
tdc_buf_next_size_size_o => (others => '0'),
tdc_buf_next_size_size_load_o => '0',
tdc_buf_next_size_valid_o => '0',
tdc_buf_next_size_valid_load_o => '0'
);
function "or" (left, right: t_TDC_BUF_in_registers) return t_TDC_BUF_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_buffer_control_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDC_BUF_in_registers;
regs_o : out t_TDC_BUF_out_registers
);
end component;
end package;
package body TDC_BUF_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_TDC_BUF_in_registers) return t_TDC_BUF_in_registers is
variable tmp: t_TDC_BUF_in_registers;
begin
tmp.tdc_buf_csr_done_i := f_x_to_zero(left.tdc_buf_csr_done_i) or f_x_to_zero(right.tdc_buf_csr_done_i);
tmp.tdc_buf_csr_overflow_i := f_x_to_zero(left.tdc_buf_csr_overflow_i) or f_x_to_zero(right.tdc_buf_csr_overflow_i);
tmp.tdc_buf_cur_base_i := f_x_to_zero(left.tdc_buf_cur_base_i) or f_x_to_zero(right.tdc_buf_cur_base_i);
tmp.tdc_buf_cur_count_i := f_x_to_zero(left.tdc_buf_cur_count_i) or f_x_to_zero(right.tdc_buf_cur_count_i);
tmp.tdc_buf_cur_size_size_i := f_x_to_zero(left.tdc_buf_cur_size_size_i) or f_x_to_zero(right.tdc_buf_cur_size_size_i);
tmp.tdc_buf_cur_size_valid_i := f_x_to_zero(left.tdc_buf_cur_size_valid_i) or f_x_to_zero(right.tdc_buf_cur_size_valid_i);
tmp.tdc_buf_next_base_i := f_x_to_zero(left.tdc_buf_next_base_i) or f_x_to_zero(right.tdc_buf_next_base_i);
tmp.tdc_buf_next_size_size_i := f_x_to_zero(left.tdc_buf_next_size_size_i) or f_x_to_zero(right.tdc_buf_next_size_size_i);
tmp.tdc_buf_next_size_valid_i := f_x_to_zero(left.tdc_buf_next_size_valid_i) or f_x_to_zero(right.tdc_buf_next_size_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/tdc_core_pkg.vhd
View file @ 1e1a8a0a
......@@ -60,6 +60,26 @@ use work.gencores_pkg.all;
--=================================================================================================
package tdc_core_pkg is
type t_raw_acam_timestamp is record
slope : std_logic;
channel : std_logic_vector(2 downto 0);
n_bins : std_logic_vector(16 downto 0);
coarse : std_logic_vector(31 downto 0);
tai : std_logic_vector(31 downto 0);
end record;
type t_tdc_timestamp is record
slope : std_logic;
channel : std_logic_vector(2 downto 0);
frac : std_logic_vector(11 downto 0);
coarse : std_logic_vector(31 downto 0);
tai : std_logic_vector(31 downto 0);
seq : std_logic_vector(31 downto 0);
end record;
type t_tdc_timestamp_array is array(integer range<>) of t_tdc_timestamp;
---------------------------------------------------------------------------------------------------
-- Constant regarding the Mezzanine DAC configuration --
---------------------------------------------------------------------------------------------------
......@@ -187,6 +207,23 @@ package tdc_core_pkg is
name => "WB-TDC-TsFIFO ")));
constant c_TDC_DMA_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"00000000000001FF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000623", -- "WB-TDC-Mem " | md5sum | cut -c1-8
version => x"00000001",
date => x"20150415",
name => "WB-TDC-TsDMAEngine ")));
---------------------------------------------------------------------------------------------------
-- Constants regarding 1 Hz pulse generation --
---------------------------------------------------------------------------------------------------
......@@ -396,12 +433,6 @@ package tdc_core_pkg is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- Input pulses arriving also to the FPGA, currently not treated
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
-- White Rabbit core
wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic;
......@@ -470,11 +501,6 @@ package tdc_core_pkg is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_synched_i : in std_logic;
......@@ -482,7 +508,7 @@ package tdc_core_pkg is
wrabbit_tai_i : in std_logic_vector(31 downto 0);
cfg_slave_i : in t_wishbone_slave_in;
cfg_slave_o : out t_wishbone_slave_out;
timestamp_o : out std_logic_vector(127 downto 0);
timestamp_o : out t_tdc_timestamp;
timestamp_stb_o : out std_logic;
channel_enable_o : out std_logic_vector(4 downto 0);
irq_threshold_o : out std_logic_vector(9 downto 0);
......@@ -910,11 +936,6 @@ package tdc_core_pkg is
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
mezz_scl_o : out std_logic;
mezz_sda_o : out std_logic;
mezz_scl_i : in std_logic;
......@@ -937,6 +958,7 @@ package tdc_core_pkg is
clk_125m_tdc_o : out std_logic);
end component fmc_tdc_wrapper;
function f_pick(cond:boolean; if_true: std_logic_vector; if_false: std_logic_vector) return std_logic_vector;
......
hdl/rtl/tdc_dma_channel.vhd 0 → 100644
View file @ 1e1a8a0a
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.tdc_core_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.tdc_buf_wbgen2_pkg.all;
entity tdc_dma_channel is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ts_i : in t_tdc_timestamp;
ts_valid_i : in std_logic;
ts_ready_o : out std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_tick_i : in std_logic;
irq_o : out std_logic;
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in
);
end tdc_dma_channel;
architecture rtl of tdc_dma_channel is
signal cur_base : unsigned(31 downto 0);
signal cur_size : unsigned(31 downto 0);
signal cur_valid : std_logic;
signal cur_pos : unsigned(31 downto 0);
signal next_base : unsigned(31 downto 0);
signal next_size : unsigned(31 downto 0);
signal next_valid : std_logic;
signal addr : unsigned(31 downto 0);
signal count : unsigned(31 downto 0);
signal burst_count : unsigned(8 downto 0);
signal irq_timer : unsigned(15 downto 0);
signal regs_out : t_TDC_BUF_out_registers;
signal regs_in : t_TDC_BUF_in_registers;
type t_STATE is (IDLE, SWITCH_BUFFERS, WAIT_NEXT_TS, SER0, SER1, SER2, SER3);
type t_DMA_STATE is (WAIT_BURST, EXECUTE_BURST, WAIT_ACKS);
signal fifo_in : std_logic_vector(33 downto 0);
alias fifo_in_data is fifo_in(31 downto 0);
alias fifo_in_is_addr is fifo_in(32);
alias fifo_in_last_in_buffer is fifo_in(33);
signal fifo_out : std_logic_vector(33 downto 0);
alias fifo_out_data is fifo_out(31 downto 0);
alias fifo_out_is_addr is fifo_out(32);
alias fifo_out_last_in_buffer is fifo_out(33);
signal fifo_rd, fifo_wr, fifo_full, fifo_empty, fifo_clear, fifo_valid : std_logic;
signal fifo_count : std_logic_vector(7 downto 0);
signal state : t_STATE;
signal dma_state : t_DMA_STATE;
signal ts : t_tdc_timestamp;
signal buffer_switch_latched : std_logic;
signal dma_addr : unsigned(31 downto 0);
signal burst_add : std_logic;
signal burst_sub : std_logic;
signal bursts_in_fifo : unsigned(3 downto 0);
signal ack_count : unsigned(5 downto 0);
signal dma_wb_out : t_wishbone_master_out;
signal irq_req : std_logic;
signal overflow : std_logic;
begin
U_WB_Regs : tdc_buffer_control_wb
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
slave_i => slave_i,
slave_o => slave_o,
-- int_o => int_o,
regs_i => regs_in,
regs_o => regs_out);
p_irq_timer : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_timer <= (others => '0');
irq_o <= '0';
else
irq_o <= '0';
if irq_req = '0' then
irq_timer <= (others => '0');
elsif irq_timer = unsigned(regs_out.tdc_buf_csr_irq_timeout_o) then
irq_o <= '1';
elsif irq_req = '1' and irq_tick_i = '1' then
irq_timer <= irq_timer + 1;
end if;
end if;
end if;
end process;
p_write_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= IDLE;
fifo_wr <= '0';
fifo_clear <= '1';
buffer_switch_latched <= '0';
cur_valid <= '0';
next_valid <= '0';
addr <= (others => '0');
count <= (others => '0');
burst_add <= '0';
ts_ready_o <= '0';
irq_req <= '0';
else
fifo_wr <= '0';
fifo_clear <= '0';
fifo_in_last_in_buffer <= '0';
fifo_in_is_addr <= '0';
burst_add <= '0';
ts_ready_o <= '0';
if(regs_out.tdc_buf_csr_switch_buffers_o = '1') then
buffer_switch_latched <= '1';
end if;
if(regs_out.tdc_buf_cur_base_load_o = '1') then
cur_base <= resize(unsigned(regs_out.tdc_buf_cur_base_o), cur_base'length);
addr <= resize(unsigned(regs_out.tdc_buf_cur_base_o), cur_base'length);
end if;
if(regs_out.tdc_buf_cur_size_size_load_o = '1') then
cur_size <= resize(unsigned(regs_out.tdc_buf_cur_size_size_o), cur_size'length);
end if;
if(regs_out.tdc_buf_cur_size_valid_load_o = '1') then
cur_valid <= regs_out.tdc_buf_cur_size_valid_o;
end if;
if(regs_out.tdc_buf_next_base_load_o = '1') then
next_base <= resize(unsigned(regs_out.tdc_buf_next_base_o), next_base'length);
end if;
if(regs_out.tdc_buf_next_size_size_load_o = '1') then
next_size <= resize(unsigned(regs_out.tdc_buf_next_size_size_o), next_size'length);
end if;
if(regs_out.tdc_buf_next_size_valid_load_o = '1') then
next_valid <= regs_out.tdc_buf_next_size_valid_o;
end if;
case state is
when SWITCH_BUFFERS =>
count <= (others => '0');
cur_base <= next_base;
cur_valid <= next_valid;
cur_size <= next_size;
addr <= next_base;
next_valid <= '0';
buffer_switch_latched <= '0';
cur_pos <= count;
fifo_in_last_in_buffer <= '1';
fifo_wr <= '1';
if(next_valid = '1') then
irq_req <= '0';
end if;
state <= IDLE;
when IDLE =>
if(buffer_switch_latched = '1') then
state <= SWITCH_BUFFERS;
end if;
if regs_out.tdc_buf_csr_enable_o = '1' and ts_valid_i = '1' then
if cur_valid = '1' then
if count < cur_size then
ts <= ts_i;
state <= SER0;
fifo_in_is_addr <= '1';
fifo_in_data <= std_logic_vector(addr);
fifo_wr <= '1';
burst_count <= (others => '0');
irq_req <= '1';
ts_ready_o <= '1';
else
buffer_switch_latched <= '1';
end if;
overflow <= '0';
else
ts_ready_o <= '1';
overflow <= '1';
end if;
end if;
when WAIT_NEXT_TS =>
fifo_in_is_addr <= '0';
if regs_out.tdc_buf_csr_enable_o = '0' or burst_count = unsigned(regs_out.tdc_buf_csr_burst_size_o) or buffer_switch_latched = '1' then
burst_add <= '1';
state <= IDLE;
elsif ts_valid_i = '1' then
state <= SER0;
ts <= ts_i;
ts_ready_o <= '1';
end if;
when SER0 =>
fifo_in_data <= ts.tai;
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= SER1;
when SER1 =>
fifo_in_data <= ts.coarse;
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= SER2;
when SER2 =>
fifo_in_data <= ts.frac & ts_i.slope & ts_i.channel & x"0000";
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= SER3;
when SER3 =>
fifo_in_data <= ts.seq;
fifo_in_is_addr <= '0';
fifo_wr <= '1';
state <= WAIT_NEXT_TS;
count <= count + 1;
addr <= addr + 16;
burst_count <= burst_count + 1;
end case;
end if;
end if;
end process;
p_burst_counter : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
bursts_in_fifo <= (others => '0');
else
if burst_add = '1' and burst_sub = '0' then
bursts_in_fifo <= bursts_in_fifo + 1;
elsif burst_add = '0' and burst_sub = '1' then
bursts_in_fifo <= bursts_in_fifo - 1;
end if;
end if;
end if;
end process;
U_FIFO : generic_sync_fifo
generic map (
g_data_width => 34,
g_size => 256,
g_show_ahead => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fifo_in,
we_i => fifo_wr,
q_o => fifo_out,
rd_i => fifo_rd,
empty_o => fifo_empty,
full_o => fifo_full,
count_o => fifo_count);
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dma_wb_out.cyc <= '0';
fifo_valid <= '0';
burst_sub <= '0';
dma_state <= WAIT_BURST;
regs_in.tdc_buf_csr_done_i <= '0';
else
burst_sub <= '0';
if regs_out.tdc_buf_csr_done_o = '1' and regs_out.tdc_buf_csr_done_load_o = '1' then
regs_in.tdc_buf_csr_done_i <= '0';
elsif fifo_empty = '0' and fifo_out_last_in_buffer = '1' then
regs_in.tdc_buf_csr_done_i <= '1';
end if;
case dma_state is
when WAIT_BURST =>
if bursts_in_fifo /= 0 and fifo_empty = '0' and fifo_out_is_addr = '1' and fifo_out_last_in_buffer = '0' then
dma_wb_out.cyc <= '1';
dma_addr <= unsigned(fifo_out_data);
dma_state <= EXECUTE_BURST;
burst_sub <= '1';
end if;
when EXECUTE_BURST =>
if fifo_rd = '1' then
dma_addr <= dma_addr + 4;
end if;
if fifo_empty = '1' then
dma_state <= WAIT_ACKS;
elsif fifo_out_is_addr = '1' and fifo_out_last_in_buffer = '0' then
dma_state <= WAIT_ACKS;
end if;
when WAIT_ACKS =>
if ack_count = 0 then
dma_wb_out.cyc <= '0';
dma_state <= WAIT_BURST;
end if;
end case;
end if;
end if;
end process;
p_fifo_control : process(dma_wb_i, bursts_in_fifo, fifo_empty, dma_state, fifo_out_is_addr, fifo_out_last_in_buffer)
begin
fifo_rd <= '0';
if (fifo_out_last_in_buffer = '1' and fifo_empty = '0') then
fifo_rd <= '1';
else
case dma_state is
when WAIT_BURST =>
if bursts_in_fifo /= 0 and fifo_empty = '0' and fifo_out_is_addr = '1' then
fifo_rd <= '1';
end if;
when EXECUTE_BURST =>
if fifo_empty = '0' and dma_wb_i.stall = '0' and fifo_out_is_addr = '0' then
fifo_rd <= '1';
end if;
when WAIT_ACKS =>
fifo_rd <= '0';
end case;
end if;
end process;
p_count_acks : process(clk_i)
begin
if rising_edge(clk_i) then
if dma_wb_out.cyc = '0' then
ack_count <= (others => '0');
elsif(dma_wb_out.cyc = '1' and dma_wb_out.stb = '1' and dma_wb_i.stall = '0' and dma_wb_i.ack = '0') then
ack_count <= ack_count + 1;
elsif((dma_wb_out.stb = '0' or dma_wb_i.stall = '1') and dma_wb_i.ack = '1') then
ack_count <= ack_count - 1;
end if;
end if;
end process;
dma_wb_out.adr <= std_logic_vector(dma_addr);
dma_wb_out.dat <= fifo_out_data;
dma_wb_out.stb <= not fifo_empty and not fifo_out_is_addr when (dma_state = EXECUTE_BURST) else '0';
dma_wb_out.we <= '1';
dma_wb_out.sel <= (others => '1');
dma_wb_o <= dma_wb_out;
regs_in.tdc_buf_cur_base_i <= std_logic_vector(resize(cur_base, 32));
regs_in.tdc_buf_cur_size_size_i <= std_logic_vector(resize(cur_size, 30));
regs_in.tdc_buf_cur_size_valid_i <= cur_valid;
regs_in.tdc_buf_next_base_i <= std_logic_vector(resize(next_base, 32));
regs_in.tdc_buf_next_size_size_i <= std_logic_vector(resize(next_size, 30));
regs_in.tdc_buf_next_size_valid_i <= next_valid;
regs_in.tdc_buf_cur_count_i <= std_logic_vector(resize(cur_pos, 32));
end rtl;
hdl/rtl/tdc_dma_channel_regs.vhd 0 → 100644
View file @ 1e1a8a0a
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Channel Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_dma_channel_regs.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_dma_channel_regs.wb
-- Created : Wed Jul 18 23:25:00 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_dma_channel_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.TDMA_wbgen2_pkg.all;
entity tdc_dma_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDMA_in_registers;
regs_o : out t_TDMA_out_registers
);
end tdc_dma_channel_wb;
architecture syn of tdc_dma_channel_wb is
signal tdma_csr_enable_int : std_logic ;
signal tdma_csr_irq_timeout_int : std_logic_vector(9 downto 0);
signal tdma_csr_burst_size_int : std_logic_vector(9 downto 0);
signal tdma_csr_switch_buffers_dly0 : std_logic ;
signal tdma_csr_switch_buffers_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tdma_csr_enable_int <= '0';
tdma_csr_irq_timeout_int <= "0000000000";
tdma_csr_burst_size_int <= "0000000000";
tdma_csr_switch_buffers_int <= '0';
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tdma_csr_switch_buffers_int <= '0';
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (slave_i.we = '1') then
tdma_csr_enable_int <= wrdata_reg(0);
tdma_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
tdma_csr_burst_size_int <= wrdata_reg(20 downto 11);
tdma_csr_switch_buffers_int <= wrdata_reg(21);
regs_o.tdma_csr_done_load_o <= '1';
regs_o.tdma_csr_overflow_load_o <= '1';
end if;
rddata_reg(0) <= tdma_csr_enable_int;
rddata_reg(10 downto 1) <= tdma_csr_irq_timeout_int;
rddata_reg(20 downto 11) <= tdma_csr_burst_size_int;
rddata_reg(21) <= '0';
rddata_reg(22) <= regs_i.tdma_csr_done_i;
rddata_reg(23) <= regs_i.tdma_csr_overflow_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_size_size_load_o <= '1';
regs_o.tdma_cur_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdma_cur_size_size_i;
rddata_reg(30) <= regs_i.tdma_cur_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (slave_i.we = '1') then
regs_o.tdma_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (slave_i.we = '1') then
regs_o.tdma_next_size_size_load_o <= '1';
regs_o.tdma_next_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdma_next_size_size_i;
rddata_reg(30) <= regs_i.tdma_next_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Enable DMA
regs_o.tdma_csr_enable_o <= tdma_csr_enable_int;
-- IRQ Timeout (ms)
regs_o.tdma_csr_irq_timeout_o <= tdma_csr_irq_timeout_int;
-- Burst size (timestamps)
regs_o.tdma_csr_burst_size_o <= tdma_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdma_csr_switch_buffers_dly0 <= '0';
regs_o.tdma_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
tdma_csr_switch_buffers_dly0 <= tdma_csr_switch_buffers_int;
regs_o.tdma_csr_switch_buffers_o <= tdma_csr_switch_buffers_int and (not tdma_csr_switch_buffers_dly0);
end if;
end process;
-- DMA complete
regs_o.tdma_csr_done_o <= wrdata_reg(22);
-- DMA overflow
regs_o.tdma_csr_overflow_o <= wrdata_reg(23);
-- Base address
regs_o.tdma_cur_base_o <= wrdata_reg(31 downto 0);
-- Number of data samples in the buffer
-- Size (in transfers)
regs_o.tdma_cur_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdma_cur_size_valid_o <= wrdata_reg(30);
-- Base address
regs_o.tdma_next_base_o <= wrdata_reg(31 downto 0);
-- Size (in transfers)
regs_o.tdma_next_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdma_next_size_valid_o <= wrdata_reg(30);
rwaddr_reg <= slave_i.adr(4 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
hdl/rtl/tdc_dma_channel_wbgen2_pkg.vhd 0 → 100644
View file @ 1e1a8a0a
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Channel Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_dma_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_dma_channel_regs.wb
-- Created : Wed Jul 18 23:25:00 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_dma_channel_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDMA_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDMA_in_registers is record
tdma_csr_done_i : std_logic;
tdma_csr_overflow_i : std_logic;
tdma_cur_base_i : std_logic_vector(31 downto 0);
tdma_cur_count_i : std_logic_vector(31 downto 0);
tdma_cur_size_size_i : std_logic_vector(29 downto 0);
tdma_cur_size_valid_i : std_logic;
tdma_next_base_i : std_logic_vector(31 downto 0);
tdma_next_size_size_i : std_logic_vector(29 downto 0);
tdma_next_size_valid_i : std_logic;
end record;
constant c_TDMA_in_registers_init_value: t_TDMA_in_registers := (
tdma_csr_done_i => '0',
tdma_csr_overflow_i => '0',
tdma_cur_base_i => (others => '0'),
tdma_cur_count_i => (others => '0'),
tdma_cur_size_size_i => (others => '0'),
tdma_cur_size_valid_i => '0',
tdma_next_base_i => (others => '0'),
tdma_next_size_size_i => (others => '0'),
tdma_next_size_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_TDMA_out_registers is record
tdma_csr_enable_o : std_logic;
tdma_csr_irq_timeout_o : std_logic_vector(9 downto 0);
tdma_csr_burst_size_o : std_logic_vector(9 downto 0);
tdma_csr_switch_buffers_o : std_logic;
tdma_csr_done_o : std_logic;
tdma_csr_done_load_o : std_logic;
tdma_csr_overflow_o : std_logic;
tdma_csr_overflow_load_o : std_logic;
tdma_cur_base_o : std_logic_vector(31 downto 0);
tdma_cur_base_load_o : std_logic;
tdma_cur_size_size_o : std_logic_vector(29 downto 0);
tdma_cur_size_size_load_o : std_logic;
tdma_cur_size_valid_o : std_logic;
tdma_cur_size_valid_load_o : std_logic;
tdma_next_base_o : std_logic_vector(31 downto 0);
tdma_next_base_load_o : std_logic;
tdma_next_size_size_o : std_logic_vector(29 downto 0);
tdma_next_size_size_load_o : std_logic;
tdma_next_size_valid_o : std_logic;
tdma_next_size_valid_load_o : std_logic;
end record;
constant c_TDMA_out_registers_init_value: t_TDMA_out_registers := (
tdma_csr_enable_o => '0',
tdma_csr_irq_timeout_o => (others => '0'),
tdma_csr_burst_size_o => (others => '0'),
tdma_csr_switch_buffers_o => '0',
tdma_csr_done_o => '0',
tdma_csr_done_load_o => '0',
tdma_csr_overflow_o => '0',
tdma_csr_overflow_load_o => '0',
tdma_cur_base_o => (others => '0'),
tdma_cur_base_load_o => '0',
tdma_cur_size_size_o => (others => '0'),
tdma_cur_size_size_load_o => '0',
tdma_cur_size_valid_o => '0',
tdma_cur_size_valid_load_o => '0',
tdma_next_base_o => (others => '0'),
tdma_next_base_load_o => '0',
tdma_next_size_size_o => (others => '0'),
tdma_next_size_size_load_o => '0',
tdma_next_size_valid_o => '0',
tdma_next_size_valid_load_o => '0'
);
function "or" (left, right: t_TDMA_in_registers) return t_TDMA_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_dma_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDMA_in_registers;
regs_o : out t_TDMA_out_registers
);
end component;
end package;
package body TDMA_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_TDMA_in_registers) return t_TDMA_in_registers is
variable tmp: t_TDMA_in_registers;
begin
tmp.tdma_csr_done_i := f_x_to_zero(left.tdma_csr_done_i) or f_x_to_zero(right.tdma_csr_done_i);
tmp.tdma_csr_overflow_i := f_x_to_zero(left.tdma_csr_overflow_i) or f_x_to_zero(right.tdma_csr_overflow_i);
tmp.tdma_cur_base_i := f_x_to_zero(left.tdma_cur_base_i) or f_x_to_zero(right.tdma_cur_base_i);
tmp.tdma_cur_count_i := f_x_to_zero(left.tdma_cur_count_i) or f_x_to_zero(right.tdma_cur_count_i);
tmp.tdma_cur_size_size_i := f_x_to_zero(left.tdma_cur_size_size_i) or f_x_to_zero(right.tdma_cur_size_size_i);
tmp.tdma_cur_size_valid_i := f_x_to_zero(left.tdma_cur_size_valid_i) or f_x_to_zero(right.tdma_cur_size_valid_i);
tmp.tdma_next_base_i := f_x_to_zero(left.tdma_next_base_i) or f_x_to_zero(right.tdma_next_base_i);
tmp.tdma_next_size_size_i := f_x_to_zero(left.tdma_next_size_size_i) or f_x_to_zero(right.tdma_next_size_size_i);
tmp.tdma_next_size_valid_i := f_x_to_zero(left.tdma_next_size_valid_i) or f_x_to_zero(right.tdma_next_size_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/tdc_dma_engine.vhd 0 → 100644
View file @ 1e1a8a0a
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.tdc_core_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.gencores_pkg.all;
entity tdc_dma_engine is
generic (
g_CLOCK_FREQ : integer := 62500000
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ts_i : in t_tdc_timestamp_array(4 downto 0);
ts_valid_i : in std_logic_vector(4 downto 0);
ts_ready_o : out std_logic_vector(4 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irq_o : out std_logic_vector(4 downto 0);
dma_wb_o : out t_wishbone_master_out;
dma_wb_i : in t_wishbone_master_in
);
end tdc_dma_engine;
architecture rtl of tdc_dma_engine is
signal cr_cnx_master_out : t_wishbone_master_out_array(4 downto 0);
signal cr_cnx_master_in : t_wishbone_master_in_array(4 downto 0);
signal dma_cnx_slave_out : t_wishbone_slave_out_array(4 downto 0);
signal dma_cnx_slave_in : t_wishbone_slave_in_array(4 downto 0);
signal c_CR_CNX_BASE_ADDR : t_wishbone_address_array(4 downto 0) :=
(0 => x"00000000",
1 => x"00000040",
2 => x"00000080",
3 => x"000000c0",
4 => x"00000100");
signal c_CR_CNX_BASE_MASK : t_wishbone_address_array(4 downto 0) :=
(0 => x"000001c0",
1 => x"000001c0",
2 => x"000001c0",
3 => x"000001c0",
4 => x"000001c0");
constant c_TIMER_PERIOD_MS : integer := 1;
constant c_TIMER_DIVIDER_VALUE : integer := g_CLOCK_FREQ * c_TIMER_PERIOD_MS / 1000 - 1;
signal irq_tick_div : unsigned(15 downto 0);
signal irq_tick : std_logic;
begin
p_irq_tick : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_tick <= '0';
irq_tick_div <= (others => '0');
else
if irq_tick_div = c_TIMER_DIVIDER_VALUE then
irq_tick <= '1';
irq_tick_div <= (others => '0');
else
irq_tick <= '0';
irq_tick_div <= irq_tick_div + 1;
end if;
end if;
end if;
end process;
U_CR_Crossbar : xwb_crossbar
generic map (
g_num_masters => 1,
g_num_slaves => 5,
g_registered => true,
g_address => c_CR_CNX_BASE_ADDR,
g_mask => c_CR_CNX_BASE_MASK)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i(0) => slave_i,
slave_o(0) => slave_o,
master_i => cr_cnx_master_in,
master_o => cr_cnx_master_out);
U_DMA_Crossbar : xwb_crossbar
generic map (
g_num_masters => 5,
g_num_slaves => 1,
g_registered => true,
g_address => (0 => x"00000000"),
g_mask => (0 => x"00000000"))
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
slave_i => dma_cnx_slave_in,
slave_o => dma_cnx_slave_out,
master_i(0) => dma_wb_i,
master_o(0) => dma_wb_o);
gen_channels : for i in 0 to 4 generate
U_DMA_Channel : entity work.tdc_dma_channel
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
ts_i => ts_i(i),
ts_valid_i => ts_valid_i(i),
ts_ready_o => ts_ready_o(i),
slave_i => cr_cnx_master_out(i),
slave_o => cr_cnx_master_in(i),
irq_o => irq_o(i),
irq_tick_i => irq_tick,
dma_wb_o => dma_cnx_slave_in(i),
dma_wb_i => dma_cnx_slave_out(i));
end generate gen_channels;
end rtl;
hdl/rtl/timestamp_convert_filter.vhd 0 → 100644
View file @ 1e1a8a0a
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.tdc_core_pkg.all;
use work.gencores_pkg.all;
entity timestamp_convert_filter is
port (
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
enable_i : in std_logic_vector(4 downto 0);
-- raw timestamp input, clk_tdc_i domain
ts_i : in t_raw_acam_timestamp;
ts_valid_i : in std_logic;
-- converted and filtered timestamp output, clk_sys_i domain
ts_o : out t_tdc_timestamp_array(4 downto 0);
ts_valid_o : out std_logic_vector(4 downto 0);
ts_ready_i : in std_logic_vector(4 downto 0)
);
end timestamp_convert_filter;
architecture rtl of timestamp_convert_filter is
constant c_MIN_PULSE_WIDTH_TICKS : integer := 12; -- 12 * 8 ns = 96 ns
constant c_FINE_SF : unsigned(17 downto 0) := to_unsigned(84934, 18);
constant c_FINE_SHIFT : integer := 11;
type t_channel_state is record
expected_edge : std_logic;
last_ts : t_tdc_timestamp;
last_valid : std_logic;
seq : unsigned(31 downto 0);
s1_delta_coarse : unsigned(31 downto 0);
s1_delta_tai : unsigned(31 downto 0);
s2_delta_coarse : unsigned(31 downto 0);
s2_delta_tai : unsigned(31 downto 0);
s1_valid, s2_valid : std_logic;
end record;
type t_channel_state_array is array(integer range<>) of t_channel_state;
signal channels : t_channel_state_array(0 to 4);
signal s1_frac_scaled : unsigned(31 downto 0);
signal s1_tai, s2_tai, s3_tai : unsigned(31 downto 0);
signal s1_valid, s2_valid, s3_valid : std_logic;
signal s1_coarse, s2_coarse, s3_coarse : unsigned(31 downto 0);
signal s2_frac, s3_frac : unsigned(11 downto 0);
signal coarse_adj : std_logic_vector(31 downto 0);
signal s1_channel, s2_channel, s3_channel : std_logic_vector(2 downto 0);
signal s1_edge, s2_edge, s3_edge : std_logic;
signal s3_ts : t_tdc_timestamp;
signal ts_valid_sys : std_logic;
begin
U_Sync_TS_Valid : gc_pulse_synchronizer2
port map (
clk_in_i => clk_tdc_i,
rst_in_n_i => rst_tdc_n_i,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_sys_n_i,
d_ready_o => open,
d_p_i => ts_valid_i,
q_p_o => ts_valid_sys);
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
s1_valid <= '0';
s2_valid <= '0';
s3_valid <= '0';
else
-- 64/125 = 4096/8000: reduce fraction to avoid 64-bit division
-- frac = hwts->bins * 81 * 64 / 125;
-- stage 1: scale frac
s1_frac_scaled <= resize ((unsigned(ts_i.n_bins) * c_FINE_SF) srl c_FINE_SHIFT, 32);
s1_coarse <= unsigned(ts_i.coarse);
s1_tai <= unsigned(ts_i.tai);
s1_edge <= ts_i.slope;
s1_channel <= ts_i.channel;
s1_valid <= ts_valid_sys;
-- stage 2: adjust coarse
s2_frac <= s1_frac_scaled(11 downto 0);
s2_coarse <= unsigned(s1_coarse) + s1_frac_scaled(31 downto 12);
s2_tai <= s1_tai;
s2_edge <= s1_edge;
s2_channel <= s1_channel;
s2_valid <= s1_valid;
-- stage 3: roll-over coarse
if s2_coarse(31) = '1' then
s3_coarse <= s2_coarse + to_unsigned(125000000, 32);
s3_tai <= s2_tai - 1;
elsif (s2_coarse >= 125000000) then
s3_coarse <= s2_coarse - to_unsigned(125000000, 32);
s3_tai <= s2_tai + 1;
else
s3_coarse <= s2_coarse;
s3_tai <= s2_tai;
end if;
s3_frac <= s2_frac;
s3_edge <= s2_edge;
s3_channel <= s2_channel;
s3_valid <= s2_valid;
end if;
end if;
end process;
s3_ts.frac <= std_logic_vector(s3_frac);
s3_ts.coarse <= std_logic_vector(s3_coarse);
s3_ts.tai <= std_logic_vector(s3_tai);
s3_ts.slope <= s3_edge;
s3_ts.channel <= s3_channel;
gen_channels : for i in 0 to 4 generate
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i(i) = '0' then
ts_valid_o(i) <= '0';
channels(i).expected_edge <= '1';
channels(i).s1_valid <= '0';
channels(i).s2_valid <= '0';
channels(i).last_valid <= '0';
channels(i).seq <= (others => '0');
else
channels(i).s1_valid <= '0';
if s3_valid = '1' and unsigned(s3_channel) = i then
-- report "s3_valid";
if (s3_ts.slope = '1') then -- rising edge
channels(i).last_ts <= s3_ts;
channels(i).last_valid <= '1';
channels(i).s1_valid <= '0';
-- report "rise";
else
channels(i).last_valid <= '0';
channels(i).s1_valid <= '1';
-- report "fall";
end if;
channels(i).s1_delta_coarse <= unsigned(s3_ts.coarse) - unsigned(channels(i).last_ts.coarse);
channels(i).s1_delta_tai <= unsigned(s3_ts.tai) - unsigned(channels(i).last_ts.tai);
end if;
if channels(i).s1_delta_coarse(31) = '1' then
channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse + to_unsigned(125000000, 32);
channels(i).s2_delta_tai <= channels(i).s1_delta_tai - 1;
else
channels(i).s2_delta_coarse <= channels(i).s1_delta_coarse;
channels(i).s2_delta_tai <= channels(i).s1_delta_tai;
end if;
channels(i).s2_valid <= channels(i).s1_valid;
if(ts_ready_i(i) = '1') then
ts_valid_o(i) <= '0';
end if;
if channels(i).s2_valid = '1' then
if channels(i).s2_delta_tai = 0 and channels(i).s2_delta_coarse >= 12 then
ts_o(i).tai <= channels(i).last_ts.tai;
ts_o(i).coarse <= channels(i).last_ts.coarse;
ts_o(i).frac <= channels(i).last_ts.frac;
ts_o(i).channel <= channels(i).last_ts.channel;
ts_o(i).slope <= channels(i).last_ts.slope;
ts_o(i).seq <= std_logic_vector(channels(i).seq);
ts_valid_o(i) <= '1';
channels(i).seq <= channels(i).seq + 1;
end if;
end if;
end if;
end if;
end process;
end generate gen_channels;
--edge = hwts->metadata & (1 << 4) ? 1 : 0;
-- /* first, convert the timestamp from the HDL units (81 ps bins)
-- to the WR format (where fractional part is 8 ns rescaled to
-- 4096 units) */
-- ts.channel = channel + 1; /* We want to see channels starting from 1*/
-- ts.seconds = hwts->utc;
-- /* 64/125 = 4096/8000: reduce fraction to avoid 64-bit division */
-- frac = hwts->bins * 81 * 64 / 125;
-- ts.coarse = hwts->coarse + frac / 4096;
-- ts.frac = frac % 4096;
-- /* the addition above may result with the coarse counter going
-- out of range: */
-- if (unlikely(ts.coarse >= 125000000)) {
-- ts.coarse -= 125000000;
-- ts.seconds++;
-- }
-- /* A trivial state machine to remove glitches, react on rising edge only
-- and drop pulses that are narrower than 100 ns.
-- We are waiting for a falling edge,
-- but a rising one occurs - ignore it.
-- */
-- if (unlikely(edge != st->expected_edge)) {
-- /* wait unconditionally for next rising edge */
-- st->expected_edge = 1;
-- return 0;
-- }
-- /* From this point we are working with the expected EDGE */
-- if (st->expected_edge == 1) {
-- /* We received a raising edge, save the time stamp and
-- wait for the falling edge */
-- st->prev_ts = ts;
-- st->expected_edge = 0;
-- return 0;
-- }
-- /* got a falling edge after a rising one */
-- diff = ts;
-- ft_ts_sub(&diff, &st->prev_ts);
-- /* Check timestamp width. Must be at least 100 ns
-- (coarse = 12, frac = 2048) */
-- if (likely(diff.seconds || diff.coarse > 12
-- || (diff.coarse == 12 && diff.frac >= 2048))) {
-- ts = st->prev_ts;
-- ft_ts_apply_offset(&ts, ft->calib.zero_offset[channel - 1]);
-- ft_ts_apply_offset(&ts, -ft->calib.wr_offset);
-- if (st->user_offset)
-- ft_ts_apply_offset(&ts, st->user_offset);
-- ts.gseq_id = ft->sequence++;
-- /* Got a dacapo flag? make a gap in the sequence ID to indicate
-- an unknown loss of timestamps */
-- ts.dseq_id = st->cur_seq_id++;
-- if (dacapo_flag) {
-- ts.dseq_id++;
-- st->cur_seq_id++;
-- }
-- ts.hseq_id = hwts->metadata >> 5;
-- /* Return a valid timestamp */
-- *wrts = ts;
-- ret = 1;
-- }
-- /* Wait for the next raising edge */
-- st->expected_edge = 1;
end rtl;
hdl/rtl/timestamp_fifo.vhd
View file @ 1e1a8a0a
......@@ -23,6 +23,7 @@ use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
use work.tsf_wbgen2_pkg.all;
use work.tdc_core_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
......@@ -32,9 +33,7 @@ entity timestamp_fifo is
);
port (
clk_sys_i : in std_logic;
clk_tdc_i : in std_logic;
rst_n_sys_i : in std_logic;
rst_tdc_i : in std_logic;
rst_sys_n_i : in std_logic;
-- WB slave, system clock
slave_i : in t_wishbone_slave_in;
......@@ -49,32 +48,14 @@ entity timestamp_fifo is
irq_threshold_i : in std_logic_vector(9 downto 0);
irq_timeout_i : in std_logic_vector(9 downto 0);
timestamp_i : in std_logic_vector(127 downto 0);
timestamp_valid_i : in std_logic
timestamp_i : in t_tdc_timestamp_array(4 downto 0);
timestamp_valid_i : in std_logic_vector(4 downto 0)
);
end entity;
architecture rtl of timestamp_fifo is
component timestamp_fifo_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_tdc_i : in std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers);
end component timestamp_fifo_wb;
signal tmr_timeout : unsigned(9 downto 0);
signal buf_irq_int : std_logic;
signal buf_count : unsigned(9 downto 0);
......@@ -86,41 +67,33 @@ architecture rtl of timestamp_fifo is
signal ts_match : std_logic;
signal seq_counter : unsigned(31 downto 0);
signal timestamp_with_seq : std_logic_vector(127 downto 0);
begin
timestamp_with_seq(95 downto 0) <= timestamp_i(95 downto 0); -- TS
timestamp_with_seq(98 downto 96) <= timestamp_i(98 downto 96); -- channel
timestamp_with_seq(100) <= timestamp_i(100); -- slope
timestamp_with_seq(127 downto 101) <= std_logic_vector(seq_counter(26 downto 0));
timestamp_with_seq(31 downto 0) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
timestamp_with_seq(63 downto 32) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
timestamp_with_seq(95 downto 64) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).frac), 32));
timestamp_with_seq(98 downto 96) <= timestamp_i(g_channel).channel;
timestamp_with_seq(100) <= timestamp_i(g_channel).slope; -- slope
timestamp_with_seq(127 downto 101) <= timestamp_i(g_channel).seq(26 downto 0);
U_WB_Slave : timestamp_fifo_wb
U_WB_Slave : entity work.timestamp_fifo_wb
port map (
rst_n_i => rst_n_sys_i,
rst_n_i => rst_sys_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => slave_i.adr(5 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
clk_tdc_i => clk_tdc_i,
slave_i => slave_i,
slave_o => slave_o,
regs_i => regs_in,
regs_o => regs_out);
buf_count <= resize(unsigned(regs_out.fifo_wr_usedw_o), 10);
ts_match <= '1' when timestamp_valid_i = '1' and unsigned(timestamp_i(98 downto 96)) = g_channel else '0';
ts_match <=timestamp_valid_i(g_channel);
p_fifo_write : process(clk_tdc_i)
p_fifo_write : process(clk_sys_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
regs_in.fifo_wr_req_i <= '0';
else
......@@ -138,23 +111,11 @@ begin
regs_in.fifo_ts2_i <= timestamp_with_seq(95 downto 64);
regs_in.fifo_ts3_i <= timestamp_with_seq(127 downto 96);
p_seq_counter : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' or regs_out.csr_rst_seq_o = '1' then
seq_counter <= (others => '0');
else
if(enable_i = '1' and ts_match = '1') then
seq_counter <= seq_counter + 1;
end if;
end if;
end if;
end process;
p_latch_last_timestamp : process(clk_tdc_i)
p_latch_last_timestamp : process(clk_sys_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
regs_in.csr_last_valid_i <= '0';
else
-- latch only the last rising edge TS
......@@ -175,10 +136,10 @@ begin
end if;
end process;
p_coalesce_irq : process(clk_tdc_i)
p_coalesce_irq : process(clk_sys_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' or enable_i = '0' then
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i = '0' then
buf_irq_int <= '0';
else
if(regs_out.fifo_wr_empty_o = '1') then
......@@ -209,11 +170,6 @@ begin
end if;
end process;
U_Sync_IRQ : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
data_i => buf_irq_int,
synced_o => irq_o);
irq_o <= buf_irq_int;
end rtl;
hdl/rtl/timestamp_fifo_wb.vhd
View file @ 1e1a8a0a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Wed Sep 20 18:41:08 2017
-- Created : Thu Jul 19 17:10:58 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
......@@ -14,27 +14,21 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.wishbone_pkg.all;
use work.tsf_wbgen2_pkg.all;
entity timestamp_fifo_wb is
port (
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_tdc_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers
);
);
end timestamp_fifo_wb;
architecture syn of timestamp_fifo_wb is
......@@ -44,48 +38,8 @@ signal tsf_fifo_in_int : std_logic_vector(127 downto 0)
signal tsf_fifo_out_int : std_logic_vector(127 downto 0);
signal tsf_fifo_rdreq_int : std_logic ;
signal tsf_fifo_rdreq_int_d0 : std_logic ;
signal tsf_lts0_int : std_logic_vector(31 downto 0);
signal tsf_lts0_lwb : std_logic ;
signal tsf_lts0_lwb_delay : std_logic ;
signal tsf_lts0_lwb_in_progress : std_logic ;
signal tsf_lts0_lwb_s0 : std_logic ;
signal tsf_lts0_lwb_s1 : std_logic ;
signal tsf_lts0_lwb_s2 : std_logic ;
signal tsf_lts1_int : std_logic_vector(31 downto 0);
signal tsf_lts1_lwb : std_logic ;
signal tsf_lts1_lwb_delay : std_logic ;
signal tsf_lts1_lwb_in_progress : std_logic ;
signal tsf_lts1_lwb_s0 : std_logic ;
signal tsf_lts1_lwb_s1 : std_logic ;
signal tsf_lts1_lwb_s2 : std_logic ;
signal tsf_lts2_int : std_logic_vector(31 downto 0);
signal tsf_lts2_lwb : std_logic ;
signal tsf_lts2_lwb_delay : std_logic ;
signal tsf_lts2_lwb_in_progress : std_logic ;
signal tsf_lts2_lwb_s0 : std_logic ;
signal tsf_lts2_lwb_s1 : std_logic ;
signal tsf_lts2_lwb_s2 : std_logic ;
signal tsf_lts3_int : std_logic_vector(31 downto 0);
signal tsf_lts3_lwb : std_logic ;
signal tsf_lts3_lwb_delay : std_logic ;
signal tsf_lts3_lwb_in_progress : std_logic ;
signal tsf_lts3_lwb_s0 : std_logic ;
signal tsf_lts3_lwb_s1 : std_logic ;
signal tsf_lts3_lwb_s2 : std_logic ;
signal tsf_csr_last_valid_int_read : std_logic ;
signal tsf_csr_last_valid_int_write : std_logic ;
signal tsf_csr_last_valid_lw : std_logic ;
signal tsf_csr_last_valid_lw_delay : std_logic ;
signal tsf_csr_last_valid_lw_read_in_progress : std_logic ;
signal tsf_csr_last_valid_lw_s0 : std_logic ;
signal tsf_csr_last_valid_lw_s1 : std_logic ;
signal tsf_csr_last_valid_lw_s2 : std_logic ;
signal tsf_csr_last_valid_rwsel : std_logic ;
signal tsf_csr_rst_seq_dly0 : std_logic ;
signal tsf_csr_rst_seq_int : std_logic ;
signal tsf_csr_rst_seq_int_delay : std_logic ;
signal tsf_csr_rst_seq_sync0 : std_logic ;
signal tsf_csr_rst_seq_sync1 : std_logic ;
signal tsf_csr_rst_seq_sync2 : std_logic ;
signal tsf_fifo_full_int : std_logic ;
signal tsf_fifo_empty_int : std_logic ;
signal tsf_fifo_clear_bus_int : std_logic ;
......@@ -93,39 +47,27 @@ signal tsf_fifo_usedw_int : std_logic_vector(8 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tsf_lts0_lwb <= '0';
tsf_lts0_lwb_delay <= '0';
tsf_lts0_lwb_in_progress <= '0';
tsf_lts1_lwb <= '0';
tsf_lts1_lwb_delay <= '0';
tsf_lts1_lwb_in_progress <= '0';
tsf_lts2_lwb <= '0';
tsf_lts2_lwb_delay <= '0';
tsf_lts2_lwb_in_progress <= '0';
tsf_lts3_lwb <= '0';
tsf_lts3_lwb_delay <= '0';
tsf_lts3_lwb_in_progress <= '0';
tsf_csr_last_valid_lw <= '0';
tsf_csr_last_valid_lw_delay <= '0';
tsf_csr_last_valid_lw_read_in_progress <= '0';
tsf_csr_last_valid_rwsel <= '0';
tsf_csr_last_valid_int_write <= '0';
regs_o.csr_last_valid_load_o <= '0';
tsf_csr_rst_seq_int <= '0';
tsf_csr_rst_seq_int_delay <= '0';
tsf_fifo_clear_bus_int <= '0';
tsf_fifo_rdreq_int <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -134,102 +76,46 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.csr_last_valid_load_o <= '0';
tsf_csr_rst_seq_int <= '0';
tsf_fifo_clear_bus_int <= '0';
ack_in_progress <= '0';
else
tsf_lts0_lwb <= tsf_lts0_lwb_delay;
tsf_lts0_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts0_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts0_int;
tsf_lts0_lwb_in_progress <= '0';
end if;
tsf_lts1_lwb <= tsf_lts1_lwb_delay;
tsf_lts1_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts1_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts1_int;
tsf_lts1_lwb_in_progress <= '0';
end if;
tsf_lts2_lwb <= tsf_lts2_lwb_delay;
tsf_lts2_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts2_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts2_int;
tsf_lts2_lwb_in_progress <= '0';
end if;
tsf_lts3_lwb <= tsf_lts3_lwb_delay;
tsf_lts3_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_lts3_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= tsf_lts3_int;
tsf_lts3_lwb_in_progress <= '0';
end if;
tsf_csr_last_valid_lw <= tsf_csr_last_valid_lw_delay;
tsf_csr_last_valid_lw_delay <= '0';
if ((ack_sreg(1) = '1') and (tsf_csr_last_valid_lw_read_in_progress = '1')) then
rddata_reg(0) <= tsf_csr_last_valid_int_read;
tsf_csr_last_valid_lw_read_in_progress <= '0';
end if;
tsf_csr_rst_seq_int <= tsf_csr_rst_seq_int_delay;
tsf_csr_rst_seq_int_delay <= '0';
regs_o.csr_last_valid_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
if (slave_i.we = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts0_lwb <= '1';
tsf_lts0_lwb_delay <= '1';
tsf_lts0_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
rddata_reg(31 downto 0) <= regs_i.lts0_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts1_lwb <= '1';
tsf_lts1_lwb_delay <= '1';
tsf_lts1_lwb_in_progress <= '1';
if (slave_i.we = '1') then
end if;
ack_sreg(5) <= '1';
rddata_reg(31 downto 0) <= regs_i.lts1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts2_lwb <= '1';
tsf_lts2_lwb_delay <= '1';
tsf_lts2_lwb_in_progress <= '1';
if (slave_i.we = '1') then
end if;
ack_sreg(5) <= '1';
rddata_reg(31 downto 0) <= regs_i.lts2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
tsf_lts3_lwb <= '1';
tsf_lts3_lwb_delay <= '1';
tsf_lts3_lwb_in_progress <= '1';
if (slave_i.we = '1') then
end if;
ack_sreg(5) <= '1';
rddata_reg(31 downto 0) <= regs_i.lts3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
tsf_csr_last_valid_int_write <= wrdata_reg(0);
tsf_csr_last_valid_lw <= '1';
tsf_csr_last_valid_lw_delay <= '1';
tsf_csr_last_valid_lw_read_in_progress <= '0';
tsf_csr_last_valid_rwsel <= '1';
if (slave_i.we = '1') then
regs_o.csr_last_valid_load_o <= '1';
tsf_csr_rst_seq_int <= wrdata_reg(1);
tsf_csr_rst_seq_int_delay <= wrdata_reg(1);
end if;
if (wb_we_i = '0') then
rddata_reg(0) <= 'X';
tsf_csr_last_valid_lw <= '1';
tsf_csr_last_valid_lw_delay <= '1';
tsf_csr_last_valid_lw_read_in_progress <= '1';
tsf_csr_last_valid_rwsel <= '0';
end if;
rddata_reg(0) <= regs_i.csr_last_valid_i;
rddata_reg(1) <= '0';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -261,10 +147,10 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
if (slave_i.we = '1') then
end if;
if (tsf_fifo_rdreq_int_d0 = '0') then
tsf_fifo_rdreq_int <= not tsf_fifo_rdreq_int;
......@@ -274,25 +160,25 @@ begin
ack_sreg(0) <= '1';
end if;
when "0110" =>
if (wb_we_i = '1') then
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(63 downto 32);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(95 downto 64);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= tsf_fifo_out_int(127 downto 96);
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
if (slave_i.we = '1') then
if (wrdata_reg(18) = '1') then
tsf_fifo_clear_bus_int <= '1';
end if;
......@@ -331,18 +217,18 @@ begin
end if;
end if;
end if;
end process;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
slave_o.dat <= rddata_reg;
-- extra code for reg/fifo/mem: Timestamp FIFO
tsf_fifo_in_int(31 downto 0) <= regs_i.fifo_ts0_i;
tsf_fifo_in_int(63 downto 32) <= regs_i.fifo_ts1_i;
tsf_fifo_in_int(95 downto 64) <= regs_i.fifo_ts2_i;
tsf_fifo_in_int(127 downto 96) <= regs_i.fifo_ts3_i;
tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int);
tsf_fifo_INST : wbgen2_fifo_async
tsf_fifo_in_int(31 downto 0) <= regs_i.fifo_ts0_i;
tsf_fifo_in_int(63 downto 32) <= regs_i.fifo_ts1_i;
tsf_fifo_in_int(95 downto 64) <= regs_i.fifo_ts2_i;
tsf_fifo_in_int(127 downto 96) <= regs_i.fifo_ts3_i;
tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int);
tsf_fifo_INST : wbgen2_fifo_sync
generic map (
g_size => 512,
g_width => 128,
......@@ -358,155 +244,48 @@ begin
rd_usedw_o => tsf_fifo_usedw_int,
rd_req_i => tsf_fifo_rdreq_int,
rst_n_i => tsf_fifo_rst_n,
wr_clk_i => clk_tdc_i,
rd_clk_i => clk_sys_i,
clk_i => clk_sys_i,
wr_data_i => tsf_fifo_in_int,
rd_data_o => tsf_fifo_out_int
);
-- Last Timestamp Word 0
-- asynchronous std_logic_vector register : Last Timestamp Word 0 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts0_lwb_s0 <= '0';
tsf_lts0_lwb_s1 <= '0';
tsf_lts0_lwb_s2 <= '0';
tsf_lts0_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts0_lwb_s0 <= tsf_lts0_lwb;
tsf_lts0_lwb_s1 <= tsf_lts0_lwb_s0;
tsf_lts0_lwb_s2 <= tsf_lts0_lwb_s1;
if ((tsf_lts0_lwb_s1 = '1') and (tsf_lts0_lwb_s2 = '0')) then
tsf_lts0_int <= regs_i.lts0_i;
end if;
end if;
end process;
-- Last Timestamp Word 1
-- Last Timestamp Word 1
-- asynchronous std_logic_vector register : Last Timestamp Word 1 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts1_lwb_s0 <= '0';
tsf_lts1_lwb_s1 <= '0';
tsf_lts1_lwb_s2 <= '0';
tsf_lts1_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts1_lwb_s0 <= tsf_lts1_lwb;
tsf_lts1_lwb_s1 <= tsf_lts1_lwb_s0;
tsf_lts1_lwb_s2 <= tsf_lts1_lwb_s1;
if ((tsf_lts1_lwb_s1 = '1') and (tsf_lts1_lwb_s2 = '0')) then
tsf_lts1_int <= regs_i.lts1_i;
end if;
end if;
end process;
-- Last Timestamp Word 2
-- Last Timestamp Word 2
-- asynchronous std_logic_vector register : Last Timestamp Word 2 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts2_lwb_s0 <= '0';
tsf_lts2_lwb_s1 <= '0';
tsf_lts2_lwb_s2 <= '0';
tsf_lts2_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts2_lwb_s0 <= tsf_lts2_lwb;
tsf_lts2_lwb_s1 <= tsf_lts2_lwb_s0;
tsf_lts2_lwb_s2 <= tsf_lts2_lwb_s1;
if ((tsf_lts2_lwb_s1 = '1') and (tsf_lts2_lwb_s2 = '0')) then
tsf_lts2_int <= regs_i.lts2_i;
end if;
end if;
-- Last Timestamp Word 3
-- Last Timestamp Word 3
-- asynchronous std_logic_vector register : Last Timestamp Word 3 (type RO/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_lts3_lwb_s0 <= '0';
tsf_lts3_lwb_s1 <= '0';
tsf_lts3_lwb_s2 <= '0';
tsf_lts3_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_tdc_i) then
tsf_lts3_lwb_s0 <= tsf_lts3_lwb;
tsf_lts3_lwb_s1 <= tsf_lts3_lwb_s0;
tsf_lts3_lwb_s2 <= tsf_lts3_lwb_s1;
if ((tsf_lts3_lwb_s1 = '1') and (tsf_lts3_lwb_s2 = '0')) then
tsf_lts3_int <= regs_i.lts3_i;
end if;
-- Last Timestamp Valid
end process;
-- Last Timestamp Valid
-- asynchronous BIT register : Last Timestamp Valid (type RW/WO, clk_tdc_i <-> clk_sys_i)
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_csr_last_valid_lw_s0 <= '0';
tsf_csr_last_valid_lw_s1 <= '0';
tsf_csr_last_valid_lw_s2 <= '0';
tsf_csr_last_valid_int_read <= '0';
regs_o.csr_last_valid_load_o <= '0';
regs_o.csr_last_valid_o <= '0';
elsif rising_edge(clk_tdc_i) then
tsf_csr_last_valid_lw_s0 <= tsf_csr_last_valid_lw;
tsf_csr_last_valid_lw_s1 <= tsf_csr_last_valid_lw_s0;
tsf_csr_last_valid_lw_s2 <= tsf_csr_last_valid_lw_s1;
if ((tsf_csr_last_valid_lw_s2 = '0') and (tsf_csr_last_valid_lw_s1 = '1')) then
if (tsf_csr_last_valid_rwsel = '1') then
regs_o.csr_last_valid_o <= tsf_csr_last_valid_int_write;
regs_o.csr_last_valid_load_o <= '1';
else
regs_o.csr_last_valid_load_o <= '0';
tsf_csr_last_valid_int_read <= regs_i.csr_last_valid_i;
end if;
else
regs_o.csr_last_valid_load_o <= '0';
regs_o.csr_last_valid_o <= wrdata_reg(0);
-- Reset Sequence Counter
end if;
end process;
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_csr_rst_seq_dly0 <= '0';
regs_o.csr_rst_seq_o <= '0';
-- Reset Sequence Counter
process (clk_tdc_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.csr_rst_seq_o <= '0';
tsf_csr_rst_seq_sync0 <= '0';
tsf_csr_rst_seq_sync1 <= '0';
tsf_csr_rst_seq_sync2 <= '0';
elsif rising_edge(clk_sys_i) then
tsf_csr_rst_seq_dly0 <= tsf_csr_rst_seq_int;
regs_o.csr_rst_seq_o <= tsf_csr_rst_seq_int and (not tsf_csr_rst_seq_dly0);
end if;
tsf_csr_rst_seq_sync0 <= tsf_csr_rst_seq_int;
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
end if;
end process;
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tsf_fifo_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
tsf_fifo_rdreq_int_d0 <= tsf_fifo_rdreq_int;
end if;
if (rst_n_i = '0') then
end process;
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 3
rwaddr_reg <= slave_i.adr(5 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
slave_o.ack <= ack_sreg(0);
end syn;
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @ 1e1a8a0a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Wed Sep 20 18:41:08 2017
-- Created : Thu Jul 19 17:10:58 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
......@@ -14,6 +14,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.wishbone_pkg.all;
package tsf_wbgen2_pkg is
......@@ -65,45 +66,62 @@ package tsf_wbgen2_pkg is
csr_last_valid_load_o => '0',
csr_rst_seq_o => '0'
);
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component timestamp_fifo_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers
);
end component;
end package;
package body tsf_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
variable tmp: t_tsf_in_registers;
variable tmp: t_tsf_in_registers;
begin
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
tmp.lts0_i := f_x_to_zero(left.lts0_i) or f_x_to_zero(right.lts0_i);
tmp.lts1_i := f_x_to_zero(left.lts1_i) or f_x_to_zero(right.lts1_i);
tmp.lts2_i := f_x_to_zero(left.lts2_i) or f_x_to_zero(right.lts2_i);
tmp.lts3_i := f_x_to_zero(left.lts3_i) or f_x_to_zero(right.lts3_i);
tmp.csr_last_valid_i := f_x_to_zero(left.csr_last_valid_i) or f_x_to_zero(right.csr_last_valid_i);
return tmp;
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
tmp.lts0_i := f_x_to_zero(left.lts0_i) or f_x_to_zero(right.lts0_i);
tmp.lts1_i := f_x_to_zero(left.lts1_i) or f_x_to_zero(right.lts1_i);
tmp.lts2_i := f_x_to_zero(left.lts2_i) or f_x_to_zero(right.lts2_i);
tmp.lts3_i := f_x_to_zero(left.lts3_i) or f_x_to_zero(right.lts3_i);
tmp.csr_last_valid_i := f_x_to_zero(left.csr_last_valid_i) or f_x_to_zero(right.csr_last_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/wbgen/tdc_buffer_control_regs.wb 0 → 100644
View file @ 1e1a8a0a
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "TDC DMA Buffer Control Registers";
prefix="TDC_BUF";
hdl_entity="tdc_buffer_control_wb";
reg {
name = "Control/Status register";
prefix = "CSR";
field {
name = "Enable acquisition";
description = "1: timestamps of the given channel will be sequentially written to the current
buffer, provided it's valid (CUR_SIZE.VALID=1)\
0: acquisition off";
prefix = "ENABLE";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "IRQ Timeout (ms)";
prefix = "IRQ_TIMEOUT";
description = "Interrupt coalescing timeout in milliseconds. Pick a high enough value to avoid too frequent interrupts and a low enough one to prevent buffer contention. 10 ms should be OK for most of the cases";
size = 10;
type = SLV;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Burst size (timestamps)";
prefix = "BURST_SIZE";
description = "Number of timestamps in a single burst to the DDR memory. Default = 16";
size = 10;
type = SLV;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Switch buffers";
description = "write 1: atomically switches the acquisition buffer from the current one (base/size in CUR_BASE/CUR_SIZE) to the next one (described in NEXT_BASE/NEXT_SIZE registers)\
write 0: no action";
prefix = "SWITCH_BUFFERS";
type = MONOSTABLE;
};
field {
name = "Burst complete";
prefix = "DONE";
description = "read 1: the current buffer has been fully committed to the DDR memory after writing 1 to SWITCH_BUFFERS field.\
read 0: still some transfers pending";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "DMA overflow";
prefix = "OVERFLOW";
description = "read 1: both the current and the next buffer have been filled with timestamps. Dropping all new incoming TS.";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Current buffer base address register";
prefix = "CUR_BASE";
field {
name = "Base address";
description = "Base address of the current buffer (in bytes) relative to the DDR3 chip (0 = first word in the memory)";
size = 32;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Current buffer base count register";
prefix = "CUR_COUNT";
field {
name = "Number of data samples";
description="Number of data samples in the buffer (1 sample = 1 timestamp)";
size = 32;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Current buffer base size/valid flag register";
prefix = "CUR_SIZE";
field {
name = "Size";
description="Number of data samples the buffer can hold (1 sample = 1 timestamp)";
prefix = "SIZE";
size = 30;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Valid flag";
prefix = "VALID";
description="write 1: indicate that this buffer is ready for acquisition and correctly configured";
size = 30;
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Next buffer base address register";
prefix = "NEXT_BASE";
field {
name = "Base address";
size = 32;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Next buffer base size/valid flag register";
prefix = "NEXT_SIZE";
field {
name = "Size (in transfers)";
prefix = "SIZE";
size = 30;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Valid flag";
prefix = "VALID";
size = 30;
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
};
hdl/rtl/wbgen/timestamp_fifo_wb.wb
View file @ 1e1a8a0a
......@@ -13,7 +13,6 @@ peripheral {
direction = CORE_TO_BUS;
prefix = "fifo";
name = "Timestamp FIFO";
clock = "clk_tdc_i";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT, FIFO_CLEAR};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
......@@ -54,7 +53,6 @@ peripheral {
field {
name = "Last Timestamp Word 0";
clock = "clk_tdc_i";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -68,7 +66,6 @@ peripheral {
field {
name = "Last Timestamp Word 1";
clock = "clk_tdc_i";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -82,7 +79,6 @@ peripheral {
field {
name = "Last Timestamp Word 2";
clock = "clk_tdc_i";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -97,7 +93,6 @@ peripheral {
field {
name = "Last Timestamp Word 3";
clock = "clk_tdc_i";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -114,7 +109,6 @@ peripheral {
field {
name = "Last Timestamp Valid";
clock = "clk_tdc_i";
prefix = "LAST_VALID";
type = BIT;
access_bus = READ_WRITE;
......@@ -124,7 +118,6 @@ peripheral {
field {
name = "Reset Sequence Counter";
clock = "clk_tdc_i";
prefix = "RST_SEQ";
type = MONOSTABLE;
};
......
hdl/syn/spec/Manifest.py
View file @ 1e1a8a0a
......@@ -12,3 +12,4 @@ syn_tool = "ise"
top_module = "wr_spec_tdc"
modules = { "local" : [ "../../top/spec" ] }
ctrls = ["bank3_32b_32b"]
hdl/syn/spec/wr_spec_tdc.xise
View file @ 1e1a8a0a
......@@ -20,8 +20,6 @@
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
......@@ -93,6 +91,7 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -132,7 +131,7 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_spec_tdc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_spec_tdc|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/wr_spec_tdc.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wr_spec_tdc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -176,7 +175,7 @@
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -342,965 +341,802 @@
<files>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../top/spec/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
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</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
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......
hdl/testbench/include/vhd_wishbone_master.svh
View file @ 1e1a8a0a
`include "simdrv_defs.svh"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
interface IVHDWishboneMaster
(
......@@ -57,3 +58,60 @@ interface IVHDWishboneMaster
endinterface // IVHDWishboneMaster
interface IVHDWishboneSlave
(
input clk_i,
input rst_n_i
);
parameter g_addr_width = 32;
parameter g_data_width = 32;
typedef virtual IWishboneSlave VIWishboneSlave;
IWishboneSlave #(g_addr_width, g_data_width) TheSlave (clk_i, rst_n_i);
t_wishbone_slave_in in;
t_wishbone_slave_out out;
modport slave
(
input in,
output out
);
assign TheSlave.cyc = in.cyc;
assign TheSlave.stb = in.stb;
assign TheSlave.we = in.we;
assign TheSlave.sel = in.sel;
assign TheSlave.adr = in.adr;
assign TheSlave.dat_i = in.dat;
assign out.ack = TheSlave.ack;
assign out.stall = TheSlave.stall;
assign out.rty = TheSlave.rty;
assign out.err = TheSlave.err;
assign out.dat = TheSlave.dat_o;
function automatic CWishboneAccessor get_accessor();
return TheSlave.get_accessor();
endfunction // get_accessor
initial begin
@(posedge rst_n_i);
@(posedge clk_i);
TheSlave.settings.mode = PIPELINED;
TheSlave.settings.stall_prob = 0.1;
TheSlave.settings.gen_random_stalls = 1;
TheSlave.settings.stall_min_duration = 1;
TheSlave.settings.stall_max_duration = 5;
end
endinterface // IVHDWishboneSlave
hdl/testbench/spec/Manifest.py
View file @ 1e1a8a0a
sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx45t"
sim_top="main"
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
include_dirs=[ "../../sim", "../include", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ]
include_dirs=[ "../../sim", "../include" ]
vcom_opt = "-mixedsvvh l"
files = [ "main.sv" ]
modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }
ctrls = ["bank3_32b_32b"]
\ No newline at end of file
hdl/testbench/spec/main.sv
View file @ 1e1a8a0a
`include "simdrv_defs.svh"
`include "gn4124_bfm.svh"
`include "timestamp_fifo_regs.vh"
module fake_acam(
input [3:0] addr,
output reg [27:0] data,
input wr,
input rd,
output reg ef1,
output reg ef2
);
typedef struct {
int channel;
time ts;
} acam_fifo_entry;
acam_fifo_entry fifo1[$], fifo2[$];
task pulse(int channel, time ts);
acam_fifo_entry ent;
ent.channel = channel % 4;
ent.ts = ts;
if (channel >= 0 && channel <= 3)
fifo1.push_back(ent);
else
fifo2.push_back(ent);
#100ns;
if(fifo1.size())
ef1 = 0;
if(fifo2.size())
ef2 = 0;
endtask // pulse
initial begin
ef1 = 1;
ef2 = 1;
data = 28'bz;
end
always@(negedge rd) begin
if (addr == 8) begin
acam_fifo_entry ent;
ent=fifo1.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else if (addr == 9) begin
acam_fifo_entry ent;
ent=fifo2.pop_front();
data <= ent.ts | (ent.channel << 26) | (1<<17);
end else
data <= 28'bz;
#10ns;
ef1 <= (fifo1.size() ? 0 : 1);
ef2 <= (fifo2.size() ? 0 : 1);
end
import wishbone_pkg::*;
import tdc_core_pkg::*;
endmodule
`include "simdrv_defs.svh"
`include "timestamp_fifo_regs.vh"
`include "if_wb_master.svh"
`include "vhd_wishbone_master.svh"
`include "acam_model.svh"
module main;
......@@ -87,7 +22,7 @@ module main;
end
reg clk_acam = 0;
reg clk_acam = 0; // 31.25 MHz
reg clk_62m5 = 0;
always@(posedge clk_125m)
......@@ -96,17 +31,57 @@ module main;
always@(posedge clk_62m5)
clk_acam <= ~clk_acam;
wire [3:0] tdc_addr;
wire [3:0] tdc_addr;
wire [27:0] tdc_data;
reg [8:1] tdc_stop = 0;
wire tdc_start, tdc_start_dis, tdc_stop_dis;
wire tdc_alutrigger = 0;
wire tdc_cs_n, tdc_oe_n, tdc_rd_n, tdc_wr_n;
wire tdc_err_flag, tdc_int_flag;
wire tdc_ef1, tdc_ef2;
tdc_gpx_model ACAM
(
.PuResN(1'b1),
.Alutrigger(tdc_alutrigger),
.RefClk(clk_acam),
.WRN(tdc_wr_n),
.RDN(tdc_rd_n),
.CSN(tdc_cs_n),
.OEN(tdc_oe_n),
.Adr(tdc_addr),
.TStart(tdc_start),
.TStop(tdc_stop),
.StartDis(tdc_start_dis),
.StopDis(tdc_stop_dis),
.IrFlag(tdc_int_flag),
.ErrFlag(tdc_err_flag),
.EF1(tdc_ef1),
.EF2(tdc_ef2),
.LF1(),
.LF2(),
.D(tdc_data)
);
IGN4124PCIMaster I_Gennum ();
wr_spec_tdc #(
.g_with_wr_phy(0),
.g_simulation(1)
.g_simulation(1),
.g_calib_soft_ip(0),
.g_sim_bypass_gennum(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
.clk_125m_pllref_n_i(~clk_125m),
......@@ -122,30 +97,37 @@ module main;
.clk_20m_vcxo_i(clk_20m),
.pll_status_i(1'b1),
.ef1_i(tdc_ef1),
.ef2_i(tdc_ef2),
.err_flag_i(1'b0),
.int_flag_i(1'b0),
.err_flag_i(tdc_err_flag),
.int_flag_i(tdc_int_flag),
.rd_n_o(tdc_rd_n),
.wr_n_o(tdc_wr_n),
.oe_n_o(tdc_oe_n),
.cs_n_o(tdc_cs_n),
.data_bus_io(tdc_data),
.address_o(tdc_addr),
.start_from_fpga_o(tdc_start),
// .start_dis_o(tdc_start_dis),
// .stop_dis_o(tdc_stop_dis),
`GENNUM_WIRE_SPEC_PINS(I_Gennum)
.sim_wb_i(Host.out),
.sim_wb_o(Host.in)
);
fake_acam ACAM(
.addr(tdc_addr),
.data(tdc_data),
.wr(1'b0),
.rd(tdc_rd_n),
.ef1(tdc_ef1),
.ef2(tdc_ef2)
);
IVHDWishboneMaster Host
(
.clk_i (DUT.clk_62m5_sys),
.rst_n_i (DUT.rst_n_sys));
assign tdc_start_dis = 0;
assign tdc_stop_dis = 0;
......@@ -157,10 +139,10 @@ module main;
CBusAccessor acc;
const uint64_t tdc1_base = 'h40000;
uint64_t d;
acc = I_Gennum.get_accessor();
acc = Host.get_accessor();
#100us;
#10us;
$display("Accessor: %x", acc);
......@@ -168,11 +150,18 @@ module main;
acc.write('h02000c, 'h3);
#500us;
#5us;
acc.read('h040000, d);
$display("TDC SDB ID : %x", d);
acc.read('h050000, d);
$display("TDC DMA R0 : %x", d);
acc.write('h045000, 'hdeadbeef);
acc.read('h045000, d);
$display("TDC Buf CSR : %x", d);
acc.write('h420a0, 1234); // set UTC
acc.write('h420fc, 1<<9); // load UTC
......@@ -186,14 +175,14 @@ module main;
acc.write('h42090, 2); // thr = 2 ts
acc.write('h42094, 10); // thr = 10 ms
$display("Start operation");
#300us;
fork
forever begin
acc.read('h45000 + `ADDR_TSF_CSR, d);
$display("TSF CSR %x", d);
// $display("TSF CSR %x", d);
if(d&1) begin
uint64_t t0,t1,t2,t3;
......@@ -209,7 +198,7 @@ module main;
end
acc.read('h45000 + `ADDR_TSF_FIFO_CSR, d);
// acc.read('h45000 + `ADDR_TSF_FIFO_CSR, d);
// $display("FIFO CSR %x", d);
/* -----\/----- EXCLUDED -----\/-----
......@@ -229,11 +218,13 @@ module main;
forever begin
$display("Pulse!");
#10us;
$display("pulse @ %t", $time);
ACAM.pulse(0, 0);
ACAM.pulse(1, 0);
ACAM.pulse(2, 0);
tdc_stop[1] <= 1;
#110ns;
tdc_stop[1] <= 0;
#10us;
end
join
......
hdl/testbench/spec/wave.do
View file @ 1e1a8a0a
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n_a_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/status_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_p_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_n_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_data_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dframe_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_valid_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_req_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rx_error_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/vc_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_p_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_n_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_data_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dframe_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_valid_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_adr_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_sel_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stb_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_we_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_cyc_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_ack_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stall_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_sel_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_we_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_cyc_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_ack_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stall_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_err_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_rty_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_int_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_clk_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_adr_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_sel_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stb_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_we_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_cyc_o
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ack_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stall_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_err_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_rty_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_int_i
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/sys_clk
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/io_clk
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/serdes_strobe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_pll_locked
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_reg
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_wbm
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_pdm
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_start
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_length
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_cid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_last
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_stat
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mrd
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mwr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpld
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpln
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_last
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_be
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr_start
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t2
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_wbm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ldm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_dframe
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_data
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_req
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_pdm_gnt
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_carrier_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_len
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_l2p
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_p2l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_next
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_done
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_error
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_byte_swap
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_abort
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_carrier_addr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_len
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_l
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_h
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_attrib
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_valid
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_s2m
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_m2s
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_sel
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_cyc
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_we
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_ack
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stall
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_adr
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_s2m
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_m2s
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_sel
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_cyc
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stb
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_we
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_ack
add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stall
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_sys_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_sys_n_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_tdc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_tdc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/acam_refclk_r_edge_p_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/send_dac_word_p_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/dac_word_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_from_fpga_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/err_flag_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/int_flag_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_dis_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/stop_dis_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/data_bus_io
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/address_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cs_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/oe_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rd_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wr_n_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef1_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef2_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/enable_inputs_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_1_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_2_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_3_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_4_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_5_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_status_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig1_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig2_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig3_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig4_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig5_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_1_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_2_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_3_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_4_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_5_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_link_up_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_time_valid_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_cycles_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_lock_en_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_locked_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_value_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_wr_p_i
add wave -noupdate -expand -group Mezz -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wb_irq_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_oen_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_oen_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/onewire_b
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_stb_o
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/general_rst_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_ref_0_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_core_wb_adr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_mem_wb_adr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_en
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_i
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_oe_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_in
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_out
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_oe_n
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_tstamp
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_to_wr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_from_wr
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_p
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_synched
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_channel
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp_stb
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/channel_enable
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_threshold
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_timeout
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tick_1ms
add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/counter_1ms
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate -group Acam /main/ACAM/PuResN
add wave -noupdate -group Acam /main/ACAM/Alutrigger
add wave -noupdate -group Acam /main/ACAM/RefClk
add wave -noupdate -group Acam /main/ACAM/WRN
add wave -noupdate -group Acam /main/ACAM/RDN
add wave -noupdate -group Acam /main/ACAM/CSN
add wave -noupdate -group Acam /main/ACAM/OEN
add wave -noupdate -group Acam /main/ACAM/Adr
add wave -noupdate -group Acam /main/ACAM/TStart
add wave -noupdate -group Acam /main/ACAM/TStop
add wave -noupdate -group Acam /main/ACAM/StartDis
add wave -noupdate -group Acam /main/ACAM/StopDis
add wave -noupdate -group Acam /main/ACAM/IrFlag
add wave -noupdate -group Acam /main/ACAM/ErrFlag
add wave -noupdate -group Acam /main/ACAM/EF1
add wave -noupdate -group Acam /main/ACAM/EF2
add wave -noupdate -group Acam /main/ACAM/LF1
add wave -noupdate -group Acam /main/ACAM/LF2
add wave -noupdate -group Acam /main/ACAM/D
add wave -noupdate -group Acam /main/ACAM/c_empty_flag_delay
add wave -noupdate -group Acam /main/ACAM/start_masked
add wave -noupdate -group Acam /main/ACAM/stop1_masked
add wave -noupdate -group Acam /main/ACAM/r_MasterAluTrig
add wave -noupdate -group Acam /main/ACAM/r_StartDisStart
add wave -noupdate -group Acam /main/ACAM/DQ
add wave -noupdate -group Acam /main/ACAM/EF1_int
add wave -noupdate -group Acam /main/ACAM/EF2_int
add wave -noupdate -group Acam /main/ACAM/start_disabled_int
add wave -noupdate -group Acam /main/ACAM/imode_start_offset
add wave -noupdate -group Acam /main/ACAM/t
add wave -noupdate -group Acam /main/ACAM/t_prev
add wave -noupdate -group Acam /main/ACAM/fifo_empty
add wave -noupdate -group Acam /main/ACAM/fifo_notempty
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_sys_n_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_n_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
......@@ -282,11 +66,6 @@ add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
......@@ -295,7 +74,8 @@ add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_ready_i
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
......@@ -353,201 +133,277 @@ add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/utc
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/raw_timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/raw_timestamp
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/final_timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/final_timestamp_ready
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/final_timestamp
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/channel_enable_int
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_sys
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
add wave -noupdate -expand -group FIFO0 -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/ts_match
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/seq_counter
add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_with_seq
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_n_i
add wave -noupdate /main/DUT/clk_125m_gtp_p_i
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/dac_sclk_o
add wave -noupdate /main/DUT/dac_din_o
add wave -noupdate /main/DUT/dac_cs1_n_o
add wave -noupdate /main/DUT/dac_cs2_n_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/carrier_scl_b
add wave -noupdate /main/DUT/carrier_sda_b
add wave -noupdate /main/DUT/carrier_onewire_b
add wave -noupdate /main/DUT/button1_i
add wave -noupdate /main/DUT/button2_i
add wave -noupdate /main/DUT/l_rst_n
add wave -noupdate /main/DUT/gpio
add wave -noupdate /main/DUT/p2l_rdy
add wave -noupdate /main/DUT/p2l_clkn
add wave -noupdate /main/DUT/p2l_clkp
add wave -noupdate /main/DUT/p2l_data
add wave -noupdate /main/DUT/p2l_dframe
add wave -noupdate /main/DUT/p2l_valid
add wave -noupdate /main/DUT/p_wr_req
add wave -noupdate /main/DUT/p_wr_rdy
add wave -noupdate /main/DUT/rx_error
add wave -noupdate /main/DUT/l2p_data
add wave -noupdate /main/DUT/l2p_dframe
add wave -noupdate /main/DUT/l2p_valid
add wave -noupdate /main/DUT/l2p_clkn
add wave -noupdate /main/DUT/l2p_clkp
add wave -noupdate /main/DUT/l2p_edb
add wave -noupdate /main/DUT/l2p_rdy
add wave -noupdate /main/DUT/l_wr_rdy
add wave -noupdate /main/DUT/p_rd_d_rdy
add wave -noupdate /main/DUT/tx_error
add wave -noupdate /main/DUT/vc_rdy
add wave -noupdate /main/DUT/pll_sclk_o
add wave -noupdate /main/DUT/pll_sdi_o
add wave -noupdate /main/DUT/pll_cs_o
add wave -noupdate /main/DUT/pll_dac_sync_o
add wave -noupdate /main/DUT/pll_sdo_i
add wave -noupdate /main/DUT/pll_status_i
add wave -noupdate /main/DUT/tdc_clk_125m_p_i
add wave -noupdate /main/DUT/tdc_clk_125m_n_i
add wave -noupdate /main/DUT/acam_refclk_p_i
add wave -noupdate /main/DUT/acam_refclk_n_i
add wave -noupdate /main/DUT/start_from_fpga_o
add wave -noupdate /main/DUT/err_flag_i
add wave -noupdate /main/DUT/int_flag_i
add wave -noupdate /main/DUT/start_dis_o
add wave -noupdate /main/DUT/stop_dis_o
add wave -noupdate /main/DUT/data_bus_io
add wave -noupdate /main/DUT/address_o
add wave -noupdate /main/DUT/cs_n_o
add wave -noupdate /main/DUT/oe_n_o
add wave -noupdate /main/DUT/rd_n_o
add wave -noupdate /main/DUT/wr_n_o
add wave -noupdate /main/DUT/ef1_i
add wave -noupdate /main/DUT/ef2_i
add wave -noupdate /main/DUT/enable_inputs_o
add wave -noupdate /main/DUT/term_en_2_o
add wave -noupdate /main/DUT/term_en_3_o
add wave -noupdate /main/DUT/term_en_4_o
add wave -noupdate /main/DUT/term_en_5_o
add wave -noupdate /main/DUT/tdc_led_status_o
add wave -noupdate /main/DUT/tdc_led_trig1_o
add wave -noupdate /main/DUT/tdc_led_trig2_o
add wave -noupdate /main/DUT/tdc_led_trig3_o
add wave -noupdate /main/DUT/tdc_led_trig4_o
add wave -noupdate /main/DUT/tdc_led_trig5_o
add wave -noupdate /main/DUT/tdc_in_fpga_1_i
add wave -noupdate /main/DUT/tdc_in_fpga_2_i
add wave -noupdate /main/DUT/tdc_in_fpga_3_i
add wave -noupdate /main/DUT/tdc_in_fpga_4_i
add wave -noupdate /main/DUT/tdc_in_fpga_5_i
add wave -noupdate /main/DUT/mezz_sys_scl_b
add wave -noupdate /main/DUT/mezz_sys_sda_b
add wave -noupdate /main/DUT/mezz_onewire_b
add wave -noupdate /main/DUT/led_red
add wave -noupdate /main/DUT/led_green
add wave -noupdate /main/DUT/pcb_ver_i
add wave -noupdate /main/DUT/prsnt_m2c_n_i
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_125m_gtp
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_62m5_sys
add wave -noupdate /main/DUT/sys_locked
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/gn_wb_adr
add wave -noupdate /main/DUT/gn4124_status
add wave -noupdate /main/DUT/carrier_owr_en
add wave -noupdate /main/DUT/carrier_owr_i
add wave -noupdate /main/DUT/irq_to_gn4124
add wave -noupdate /main/DUT/tm_link_up
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm_dac_wr_p
add wave -noupdate /main/DUT/tm_tai
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/tm_dac_value
add wave -noupdate /main/DUT/tm_dac_value_reg
add wave -noupdate /main/DUT/tm_clk_aux_lock_en
add wave -noupdate /main/DUT/tm_clk_aux_locked
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/wrc_scl_out
add wave -noupdate /main/DUT/wrc_scl_in
add wave -noupdate /main/DUT/wrc_sda_out
add wave -noupdate /main/DUT/wrc_sda_in
add wave -noupdate /main/DUT/tdc_scl_out
add wave -noupdate /main/DUT/tdc_scl_in
add wave -noupdate /main/DUT/tdc_sda_out
add wave -noupdate /main/DUT/tdc_sda_in
add wave -noupdate /main/DUT/tdc_scl_oen
add wave -noupdate /main/DUT/tdc_sda_oen
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/wrc_owr_en
add wave -noupdate /main/DUT/wrc_owr_in
add wave -noupdate /main/DUT/tdc0_irq
add wave -noupdate /main/DUT/tdc0_clk_125m
add wave -noupdate /main/DUT/tdc0_soft_rst_n
add wave -noupdate /main/DUT/powerup_rst_cnt
add wave -noupdate /main/DUT/carrier_info_fmc_rst
add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_sys_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_sys_n_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_tdc_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_tdc_n_i
add wave -noupdate -group Regs -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_i
add wave -noupdate -group Regs -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_rdbk_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo1_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo2_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_start01_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/local_utc_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/core_status_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_code_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_status_reg_i
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/activate_acq_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_acq_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_wr_config_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_config_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rst_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_status_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_start01_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/load_utc_p_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase_o
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ctrl_reg
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clear_ctrl_reg
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_en
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_c
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe1
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb1
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb2
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb3
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe0
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe1
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe2
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe3
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cyc_in_progress
add wave -noupdate -group Regs -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_in
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_out
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cc_rst_n
add wave -noupdate -group Regs /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cc_rst_n_or_sys
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/clk_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_refclk_r_edge_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/utc_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/state_active_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/activate_acq_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/deactivate_acq_p_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_i
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_from_fpga_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/stop_dis_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_r_edge_p_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_f_edge_p_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p_o
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_synch
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_synch
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_pulse
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_utc
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_n
add wave -noupdate -group Timecontrol /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_state_active
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/clk_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rst_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/data_bus_io
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/cyc_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/stb_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/we_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/adr_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/dat_i
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_meta_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_meta_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/adr_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/cs_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/oe_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rd_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr_n_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ack_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/dat_o
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/acam_data_st
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/nxt_acam_data_st
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef1_synch
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ef2_synch
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/ack
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rd
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/rd_extend
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr_extend
add wave -noupdate -group Datablk /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_data_block/wr_remove
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/clk_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/rst_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/activate_acq_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/deactivate_acq_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_wr_config_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rst_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_config_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_status_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo1_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo2_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_start01_p_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_meta_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_meta_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ack_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/start_from_fpga_i
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/state_active_p_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo1_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo2_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_ok_p_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_ok_p_o
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/nxt_engine_st
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/config_adr_c
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/reset_word
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_reg4
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_full_p
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_en
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_rst
add wave -noupdate -group DataEng /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/clk_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/rst_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp1_ok_p_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp1_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp2_ok_p_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_tstamp2_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/utc_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_incr_recent_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/clk_i_cycles_offset_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_nb_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/retrig_nb_offset_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/utc_p_i
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/timestamp_o
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/timestamp_valid_o
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_channel
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_slope
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_fine_timestamp
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_clk_i_cycles_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_roll_over
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_nb_of_retrig
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_nb_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_nb_of_cycles
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_32
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/full_timestamp
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/metadata
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/utc
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/coarse_time
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/fine_time
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_on_first_retrig_case1
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_on_first_retrig_case2
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/coarse_zero
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_clk_i_cycles_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_retrig_nb_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_current_retrig_nb_offset
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_current_roll_over_nb
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_current_retrig_from_roll_over
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_fine_time
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/previous_utc
add wave -noupdate -group DataFmt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/timestamp_valid_int
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/clk_tdc_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/rst_tdc_n_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/clk_sys_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/rst_sys_n_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/enable_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_valid_i
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_o
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_valid_o
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_ready_i
add wave -noupdate -group FilterAndCvt -expand -subitemconfig {/main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/channels(0) -expand} /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/channels
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_frac_scaled
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_tai
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_tai
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_tai
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_valid
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_valid
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_valid
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_coarse
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_coarse
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_coarse
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_frac
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_frac
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/coarse_adj
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_channel
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_channel
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_channel
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s1_edge
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s2_edge
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_edge
add wave -noupdate -group FilterAndCvt -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/s3_ts
add wave -noupdate -group FilterAndCvt /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/U_FilterAndConvert/ts_valid_sys
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/clk_sys_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/rst_sys_n_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/slave_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/slave_o
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/irq_o
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/enable_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/tick_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/irq_threshold_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/irq_timeout_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/timestamp_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/timestamp_valid_i
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/tmr_timeout
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/buf_irq_int
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/buf_count
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/last_ts
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/regs_in
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/regs_out
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/channel_id
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/ts_match
add wave -noupdate -expand -group fifo0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_without_dma_readout/gen_fifos(0)/U_TheFifo/timestamp_with_seq
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {916212143 ps} 0}
WaveRestoreCursors {{Cursor 1} {648894565 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -562,4 +418,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {3698688 ns}
WaveRestoreZoom {0 ps} {2097152 ns}
hdl/top/spec/Manifest.py
View file @ 1e1a8a0a
......@@ -8,7 +8,8 @@ modules = {
"local" : [ "../../rtl/",
"../../ip_cores/gn4124-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"
"../../ip_cores/wr-cores",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/wr_spec_tdc.ucf
View file @ 1e1a8a0a
......@@ -394,15 +394,127 @@ NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "DDR3_CAS_N" LOC = M4;
NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_CK_N" LOC = K3;
NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CK_P" LOC = K4;
NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_CKE" LOC = F2;
NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDM" LOC = N4;
NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_LDQS_N" LOC = N1;
NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_LDQS_P" LOC = N3;
NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_ODT" LOC = L6;
NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
NET "DDR3_RAS_N" LOC = M5;
NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RESET_N" LOC = E3;
NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDM" LOC = P3;
NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
NET "DDR3_UDQS_N" LOC = V1;
NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_UDQS_P" LOC = V2;
NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
NET "DDR3_WE_N" LOC = H2;
NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
NET "DDR3_RZQ" LOC = K7;
NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
NET "DDR3_ZIO" LOC = M7;
NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[0]" LOC = K2;
NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[1]" LOC = K1;
NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[2]" LOC = K5;
NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[3]" LOC = M6;
NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[4]" LOC = H3;
NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[5]" LOC = M3;
NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[6]" LOC = L4;
NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[7]" LOC = K6;
NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[8]" LOC = G3;
NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[9]" LOC = G1;
NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[10]" LOC = J4;
NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[11]" LOC = E1;
NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[12]" LOC = F1;
NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_A[13]" LOC = J6;
NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[14]" LOC = H5;
#NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[0]" LOC = J3;
NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[1]" LOC = J1;
NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_BA[2]" LOC = H1;
NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[0]" LOC = R3;
NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[1]" LOC = R1;
NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[2]" LOC = P2;
NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[3]" LOC = P1;
NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[4]" LOC = L3;
NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[5]" LOC = L1;
NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[6]" LOC = M2;
NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[7]" LOC = M1;
NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[8]" LOC = T2;
NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[9]" LOC = T1;
NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[10]" LOC = U3;
NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[11]" LOC = U1;
NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[12]" LOC = W3;
NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[13]" LOC = W1;
NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[14]" LOC = Y2;
NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
NET "DDR3_DQ[15]" LOC = Y1;
NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#===============================================================================
# Terminations
#===============================================================================
# DDR3
NET "DDR3_DQ[*]" IN_TERM = NONE;
NET "DDR3_LDQS_P" IN_TERM = NONE;
NET "DDR3_LDQS_N" IN_TERM = NONE;
NET "DDR3_UDQS_P" IN_TERM = NONE;
NET "DDR3_UDQS_N" IN_TERM = NONE;
#----------------------------------------
# False Path
#----------------------------------------
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "clk_62m5_sys" TNM_NET = clk_62m5_sys;
......@@ -416,17 +528,23 @@ TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_62m5_sys" 10ns DATAPATHONLY;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
TIMESPEC TS_RXTS = FROM "rx_ts_trig" TO "FFS" 2 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/05/19
NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2018/07/17
NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_gen_with_gennum_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "gen_with_gennum.cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "*/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
hdl/top/spec/wr_spec_tdc.vhd
View file @ 1e1a8a0a
......@@ -127,6 +127,7 @@ use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_xilinx_pkg.all;
use work.ddr3_ctrl_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -134,11 +135,16 @@ use UNISIM.vcomponents.all;
--=================================================================================================
-- Entity declaration for wr_spec_tdc
--=================================================================================================
--=================================================================================================en
entity wr_spec_tdc is
generic
(g_with_wr_phy : boolean := true;
g_simulation : boolean := false); -- this generic is set to TRUE
g_simulation : boolean := false;
g_CALIB_SOFT_IP : boolean := true;
g_sim_bypass_gennum : boolean := false;
g_use_dma_readout : boolean := true;
g_use_fake_timestamps_for_sim : boolean := false
); -- this generic is set to TRUE
-- when instantiated in a test-bench
port
( -- SPEC carrier
......@@ -178,6 +184,27 @@ entity wr_spec_tdc is
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
-- DDR3 interface
DDR3_CAS_N : out std_logic;
DDR3_CK_N : out std_logic;
DDR3_CK_P : out std_logic;
DDR3_CKE : out std_logic;
DDR3_LDM : out std_logic;
DDR3_LDQS_N : inout std_logic;
DDR3_LDQS_P : inout std_logic;
DDR3_ODT : out std_logic;
DDR3_RAS_N : out std_logic;
DDR3_RESET_N : out std_logic;
DDR3_UDM : out std_logic;
DDR3_UDQS_N : inout std_logic;
DDR3_UDQS_P : inout std_logic;
DDR3_WE_N : out std_logic;
DDR3_DQ : inout std_logic_vector(15 downto 0);
DDR3_A : out std_logic_vector(13 downto 0);
DDR3_BA : out std_logic_vector(2 downto 0);
DDR3_ZIO : inout std_logic;
DDR3_RZQ : inout std_logic;
------------------------------------------------------------------------
-- GN4124 PCI bridge pins
------------------------------------------------------------------------
......@@ -279,7 +306,17 @@ entity wr_spec_tdc is
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
-- Mezzanine presence (active low)
prsnt_m2c_n_i : in std_logic
-- Bypass GN4124 core, useful only in simulation
-- synthesis translate_off
;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
-- synthesis translate_on
);
end wr_spec_tdc;
......@@ -322,11 +359,12 @@ architecture rtl of wr_spec_tdc is
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 4;
constant c_NUM_WB_MASTERS : integer := 5;
constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
constant c_SLAVE_WRCORE : integer := 3; -- White Rabbit PTP core
constant c_WB_SLAVE_DMA : integer := 3;
constant c_SLAVE_WRCORE : integer := 4; -- White Rabbit PTP core
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......@@ -338,20 +376,39 @@ architecture rtl of wr_spec_tdc is
constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
constant c_wb_dma_ctrl_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000601",
version => x"00000001",
date => x"20121116",
name => "WB-DMA.Control ")));
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
3 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
3 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00050000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
5 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
(0 => x"00043000");
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00043000",
1 => x"00043001");
---------------------------------------------------------------------------------------------------
-- Signals --
......@@ -410,9 +467,64 @@ architecture rtl of wr_spec_tdc is
signal tdc0_clk_125m : std_logic;
signal tdc0_soft_rst_n : std_logic;
signal ddr3_tdc_adr: std_logic_vector(31 downto 0);
signal powerup_rst_cnt : unsigned(7 downto 0) := "00000000";
signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
-- GN4124 core DMA port to DDR wishbone bus
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector(31 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
signal wb_dma_sel : std_logic_vector(3 downto 0);
signal wb_dma_cyc : std_logic;
signal wb_dma_stb : std_logic;
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic;
signal wb_dma_stall : std_logic;
signal wb_dma_err : std_logic;
signal wb_dma_rty : std_logic;
signal wb_dma_int : std_logic;
signal tdc_dma_out : t_wishbone_master_out;
signal tdc_dma_in : t_wishbone_master_in;
signal ddr_clk_buf, ddr_clk : std_logic;
signal ddr3_calib_done : std_logic;
signal dma_irq : std_logic_vector(1 downto 0);
signal ddr_wr_fifo_empty : std_logic;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0));
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
signal control0 : std_logic_vector(35 downto 0);
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal ddr3_status : std_logic_vector(31 downto 0);
function f_to_string(x : boolean) return string is
begin
if x then
return "TRUE";
else
return "FALSE";
end if;
end f_to_string;
signal dma_reg_adr : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -446,7 +558,7 @@ begin
CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_DIVIDE => 3, -- 333 MHz DDR clock
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
......@@ -455,7 +567,7 @@ begin
(CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
......@@ -464,6 +576,10 @@ begin
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_20m_vcxo);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
port map
......@@ -746,6 +862,8 @@ begin
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
gen_with_gennum : if g_sim_bypass_gennum = false generate
cmp_gn4124_core : gn4124_core
port map
(rst_n_a_i => l_rst_n,
......@@ -782,7 +900,7 @@ begin
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
dma_irq_o => open,
dma_irq_o => dma_irq,
irq_p_i => '0',
irq_p_o => open,
......@@ -800,39 +918,57 @@ begin
csr_err_i => '0',
csr_rty_i => '0',
csr_int_i => '0',
-- DMA: not used
dma_clk_i => clk_62m5_sys,
dma_adr_o => open,
dma_cyc_o => open,
dma_dat_o => open,
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_ack_i => '1',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0',
dma_int_i => '0',
dma_adr_o => wb_dma_adr,
dma_dat_o => wb_dma_dat_o,
dma_sel_o => wb_dma_sel,
dma_stb_o => wb_dma_stb,
dma_we_o => wb_dma_we,
dma_cyc_o => wb_dma_cyc,
dma_dat_i => wb_dma_dat_i,
dma_ack_i => wb_dma_ack,
dma_stall_i => wb_dma_stall,
dma_err_i => wb_dma_err,
dma_rty_i => wb_dma_rty,
dma_int_i => wb_dma_int,
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => clk_62m5_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
dma_reg_dat_o => open,
dma_reg_ack_o => open,
dma_reg_stall_o => open);
dma_reg_adr_i => dma_reg_adr,
dma_reg_dat_i => cnx_master_out(c_WB_SLAVE_DMA).dat,
dma_reg_sel_i => cnx_master_out(c_WB_SLAVE_DMA).sel,
dma_reg_stb_i => cnx_master_out(c_WB_SLAVE_DMA).stb,
dma_reg_we_i => cnx_master_out(c_WB_SLAVE_DMA).we,
dma_reg_cyc_i => cnx_master_out(c_WB_SLAVE_DMA).cyc,
dma_reg_dat_o => cnx_master_in(c_WB_SLAVE_DMA).dat,
dma_reg_ack_o => cnx_master_in(c_WB_SLAVE_DMA).ack,
dma_reg_stall_o => cnx_master_in(c_WB_SLAVE_DMA).stall
);
dma_reg_adr <= "00" & cnx_master_out(c_WB_SLAVE_DMA).adr(31 downto 2);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
cmp_tdc_mezzanine : fmc_tdc_wrapper
end generate gen_with_gennum;
gen_without_gennum : if g_sim_bypass_gennum generate
-- synthesis translate_off
cnx_slave_in(c_MASTER_GENNUM) <= sim_wb_i;
sim_wb_o <= cnx_slave_out(c_MASTER_GENNUM);
wb_dma_cyc <= '0';
-- synthesis translate_on
end generate gen_without_gennum;
cmp_tdc_mezzanine : entity work.fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false)
g_with_direct_readout => false,
g_use_dma_readout => g_use_dma_readout)
port map (
clk_sys_i => clk_62m5_sys,
rst_sys_n_i => rst_n_sys,
......@@ -872,11 +1008,6 @@ begin
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
tdc_in_fpga_1_i => tdc_in_fpga_1_i,
tdc_in_fpga_2_i => tdc_in_fpga_2_i,
tdc_in_fpga_3_i => tdc_in_fpga_3_i,
tdc_in_fpga_4_i => tdc_in_fpga_4_i,
tdc_in_fpga_5_i => tdc_in_fpga_5_i,
mezz_scl_o => tdc_scl_oen,
mezz_sda_o => tdc_sda_oen,
mezz_scl_i => tdc_scl_in,
......@@ -893,6 +1024,8 @@ begin
tm_dac_wr_i => tm_dac_wr_p,
slave_i => cnx_master_out(c_WB_SLAVE_TDC),
slave_o => cnx_master_in(c_WB_SLAVE_TDC),
dma_wb_o => tdc_dma_out,
dma_wb_i => tdc_dma_in,
irq_o => tdc0_irq,
clk_125m_tdc_o => tdc0_clk_125m);
......@@ -904,7 +1037,7 @@ begin
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_62m5_sys,
......@@ -912,6 +1045,7 @@ begin
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => tdc0_irq,
irqs_i(1) => dma_irq(0),
irq_master_o => irq_to_gn4124);
gpio(0) <= irq_to_gn4124;
......@@ -941,7 +1075,7 @@ begin
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => sys_locked,
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_ddr3_cal_done_i => ddr3_calib_done,
carrier_info_stat_reserved_i => x"0000000",
carrier_info_ctrl_led_green_o => open,
......@@ -953,6 +1087,137 @@ begin
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => carrier_info_fmc_rst);
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "SPEC_BANK3_32B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => f_to_string(g_SIMULATION),
g_CALIB_SOFT_IP => f_to_string(g_CALIB_SOFT_IP),
g_P0_MASK_SIZE => 4,
g_P0_DATA_PORT_SIZE => 32,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => rst_n_sys,
status_o => ddr3_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
ddr3_ba_o => DDR3_BA,
ddr3_ras_n_o => DDR3_RAS_N,
ddr3_cas_n_o => DDR3_CAS_N,
ddr3_we_n_o => DDR3_WE_N,
ddr3_odt_o => DDR3_ODT,
ddr3_rst_n_o => DDR3_RESET_N,
ddr3_cke_o => DDR3_CKE,
ddr3_dm_o => DDR3_LDM,
ddr3_udm_o => DDR3_UDM,
ddr3_dqs_p_b => DDR3_LDQS_P,
ddr3_dqs_n_b => DDR3_LDQS_N,
ddr3_udqs_p_b => DDR3_UDQS_P,
ddr3_udqs_n_b => DDR3_UDQS_N,
ddr3_clk_p_o => DDR3_CK_P,
ddr3_clk_n_o => DDR3_CK_N,
ddr3_rzq_b => DDR3_RZQ,
ddr3_zio_b => DDR3_ZIO,
wb0_rst_n_i => rst_n_sys,
wb0_clk_i => clk_62m5_sys,
wb0_sel_i => tdc_dma_out.sel,
wb0_cyc_i => tdc_dma_out.cyc,
wb0_stb_i => tdc_dma_out.stb,
wb0_we_i => tdc_dma_out.we,
wb0_addr_i => ddr3_tdc_adr,
wb0_data_i => tdc_dma_out.dat,
wb0_data_o => open,
wb0_ack_o => tdc_dma_in.ack,
wb0_stall_o => tdc_dma_in.stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_n_sys,
wb1_clk_i => clk_62m5_sys,
wb1_sel_i => wb_dma_sel,
wb1_cyc_i => wb_dma_cyc,
wb1_stb_i => wb_dma_stb,
wb1_we_i => wb_dma_we,
wb1_addr_i => wb_dma_adr,
wb1_data_i => wb_dma_dat_o,
wb1_data_o => wb_dma_dat_i,
wb1_ack_o => wb_dma_ack,
wb1_stall_o => wb_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr3_tdc_adr <= "00" & tdc_dma_out.adr(31 downto 2);
CS_ICON : chipscope_icon
port map (
CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_62m5_sys,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
trig0(0) <= ddr3_calib_done;
trig0(1) <= wb_dma_cyc;
trig0(2) <= wb_dma_we;
trig0(3) <= wb_dma_stb;
trig0(4) <= wb_dma_ack;
trig0(5) <= wb_dma_stall;
trig0(6) <= irq_to_gn4124;
trig0(7) <= tdc0_irq;
trig0(8) <= dma_irq(0);
trig1 <= wb_dma_dat_o;
trig2 <= wb_dma_dat_i;
trig3 <= wb_dma_adr;
ddr3_calib_done <= ddr3_status(0);
-- unused Wishbone signals
wb_dma_err <= '0';
wb_dma_rty <= '0';
wb_dma_int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
......
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