Skip to content

F
FMC TDC 1ns 5cha - Gateware
Commit 182ada36 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

wip svec with convention

parent 745e912c
Hide whitespace changes
Inline Side-by-side
Showing with 840 additions and 1297 deletions
hdl/top/svec/Manifest.py
View file @ 182ada36
files = ["synthesis_descriptor.vhd",
"wr_svec_tdc.ucf",
files = ["wr_svec_tdc.ucf",
"wr_svec_tdc.vhd"];
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../rtl/",
"../../ip_cores/vme64x-core",
"local" : [
"../../rtl/",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/svec"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git"
],
"../../ip_cores/wr-cores/board/svec",
"../../ip_cores/svec",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/svec/wr_svec_tdc.ucf
View file @ 182ada36
#----------------------------------------
# FMC1/FMC2 detection
#----------------------------------------
NET "tdc1_prsntm2c_n_i" LOC = N30;
NET "tdc2_prsntm2c_n_i" LOC = AE29;
NET "tdc1_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
NET "tdc2_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
#----------------------------------------
#----------------------------------------
#
NET "fp_gpio1_o" LOC = T28;
#NET "fp_gpio2_o" LOC = R30;
#NET "fp_gpio3_i" LOC = V27;
#NET "fp_gpio4_i" LOC = U29;
NET "fp_gpio1_a2b_o" LOC = T30;
#NET "fp_gpio2_a2b_o" LOC = R29;
#NET "fp_gpio34_a2b_o" LOC = V28;
NET "fp_term_en_o[1]" LOC = AB1;
NET "fp_term_en_o[2]" LOC = W5;
NET "fp_term_en_o[3]" LOC = W4;
NET "fp_term_en_o[4]" LOC = V4;
NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio2_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio3_i" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio4_i" IOSTANDARD = "LVCMOS33";
NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[1]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[2]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[3]" IOSTANDARD = "LVCMOS33";
NET "fp_term_en_o[4]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC1/FMC2 I2C
#----------------------------------------
NET "tdc1_scl_b" LOC = P28;
NET "tdc1_sda_b" LOC = P30;
NET "tdc2_scl_b" LOC = W29;
NET "tdc2_sda_b" LOC = V30;
NET "tdc1_scl_b" IOSTANDARD = LVCMOS33;
NET "tdc1_sda_b" IOSTANDARD = LVCMOS33;
NET "tdc2_scl_b" IOSTANDARD = LVCMOS33;
NET "tdc2_sda_b" IOSTANDARD = LVCMOS33;
#----------------------------------------
# Carrier 1-Wire
#----------------------------------------
NET "carrier_onewire_b" LOC = AC30;
NET "carrier_onewire_b" IOSTANDARD = LVCMOS33;
#----------------------------------------
# SPI FLASH
#----------------------------------------
NET "spi_ncs_o" LOC = AG27;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
NET "spi_sclk_o" LOC = AG26;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
NET "spi_mosi_o" LOC = AH26;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
NET "spi_miso_i" LOC = AH27;
NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB version
#----------------------------------------
NET "pcb_ver_i[0]" LOC = AD20;
NET "pcb_ver_i[1]" LOC = AE20;
NET "pcb_ver_i[2]" LOC = AD18;
NET "pcb_ver_i[3]" LOC = AE17;
NET "pcb_ver_i[0]" IOSTANDARD = LVCMOS33;
NET "pcb_ver_i[1]" IOSTANDARD = LVCMOS33;
NET "pcb_ver_i[2]" IOSTANDARD = LVCMOS33;
NET "pcb_ver_i[3]" IOSTANDARD = LVCMOS33;
#----------------------------------------
# SVEC front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[0]" IOSTANDARD = LVCMOS33;
NET "fp_led_line_oen_o[1]" IOSTANDARD = LVCMOS33;
NET "fp_led_line_o[0]" IOSTANDARD = LVCMOS33;
NET "fp_led_line_o[1]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[0]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[1]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[2]" IOSTANDARD = LVCMOS33;
NET "fp_led_column_o[3]" IOSTANDARD = LVCMOS33;
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_rst_n_i" LOC = P4;
#NET "vme_sysclk_i" LOC = P3;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_ga_i[5]" LOC = M6;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_o[6]" LOC = R7;
NET "vme_irq_o[5]" LOC = AH2;
NET "vme_irq_o[4]" LOC = AF2;
NET "vme_irq_o[3]" LOC = N9;
NET "vme_irq_o[2]" LOC = N10;
NET "vme_irq_o[1]" LOC = AH4;
NET "vme_irq_o[0]" LOC = AG4;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = LVCMOS33;
NET "vme_rst_n_i" IOSTANDARD = LVCMOS33;
#NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = LVCMOS33;
NET "vme_retry_n_o" IOSTANDARD = LVCMOS33;
NET "vme_lword_n_b" IOSTANDARD = LVCMOS33;
NET "vme_iackout_n_o" IOSTANDARD = LVCMOS33;
NET "vme_iackin_n_i" IOSTANDARD = LVCMOS33;
NET "vme_iack_n_i" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[5]" IOSTANDARD = LVCMOS33;
NET "vme_dtack_oe_o" IOSTANDARD = LVCMOS33;
NET "vme_dtack_n_o" IOSTANDARD = LVCMOS33;
NET "vme_ds_n_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ds_n_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_data_oe_n_o" IOSTANDARD = LVCMOS33;
NET "vme_data_dir_o" IOSTANDARD = LVCMOS33;
NET "vme_berr_o" IOSTANDARD = LVCMOS33;
NET "vme_as_n_i" IOSTANDARD = LVCMOS33;
NET "vme_addr_oe_n_o" IOSTANDARD = LVCMOS33;
NET "vme_addr_dir_o" IOSTANDARD = LVCMOS33;
NET "vme_irq_o[6]" IOSTANDARD = LVCMOS33;
NET "vme_irq_o[5]" IOSTANDARD = LVCMOS33;
NET "vme_irq_o[4]" IOSTANDARD = LVCMOS33;
NET "vme_irq_o[3]" IOSTANDARD = LVCMOS33;
NET "vme_irq_o[2]" IOSTANDARD = LVCMOS33;
NET "vme_irq_o[1]" IOSTANDARD = LVCMOS33;
NET "vme_irq_o[0]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[31]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[30]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[29]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[28]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[27]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[26]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[25]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[24]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[23]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[22]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[21]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[20]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[19]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[18]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[17]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[16]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[15]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[14]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[13]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[12]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[11]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[10]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[9]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[8]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[7]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[6]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[5]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[4]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[3]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[2]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[1]" IOSTANDARD = LVCMOS33;
NET "vme_data_b[0]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[5]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[4]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[3]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[2]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[1]" IOSTANDARD = LVCMOS33;
NET "vme_am_i[0]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[31]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[30]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[29]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[28]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[27]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[26]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[25]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[24]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[23]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[22]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[21]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[20]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[19]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[18]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[17]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[16]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[15]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[14]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[13]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[12]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[11]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[10]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[9]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[8]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[7]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[6]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[5]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[4]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[3]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[2]" IOSTANDARD = LVCMOS33;
NET "vme_addr_b[1]" IOSTANDARD = LVCMOS33;
#----------------------------------------
# FMC1
# FMC0
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "tdc1_acam_refclk_p_i" LOC = H15;
NET "tdc1_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "tdc1_acam_refclk_n_i" LOC = G15;
NET "tdc1_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "tdc1_125m_clk_p_i" LOC = E16;
NET "tdc1_125m_clk_p_i" IOSTANDARD = LVDS_25;
NET "tdc1_125m_clk_n_i" LOC = D16;
NET "tdc1_125m_clk_n_i" IOSTANDARD = LVDS_25;
NET "tdc1_led_trig1_o" LOC = H13;
NET "tdc1_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig2_o" LOC = H11;
NET "tdc1_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig3_o" LOC = G11;
NET "tdc1_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_1_o" LOC = C16;
NET "tdc1_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_2_o" LOC = A16;
NET "tdc1_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "tdc1_ef1_i" LOC = F19;
NET "tdc1_ef1_i" IOSTANDARD = LVCMOS25;
NET "tdc1_ef2_i" LOC = E19;
NET "tdc1_ef2_i" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_3_o" LOC = F15;
NET "tdc1_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_4_o" LOC = E15;
NET "tdc1_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "tdc1_term_en_5_o" LOC = F13;
NET "tdc1_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_status_o" LOC = E13;
NET "tdc1_led_status_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig4_o" LOC = L11;
NET "tdc1_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "tdc1_led_trig5_o" LOC = K11;
NET "tdc1_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_sclk_o" LOC = M15;
NET "tdc1_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_dac_sync_n_o" LOC = K15;
NET "tdc1_pll_dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_cs_n_o" LOC = L14;
NET "tdc1_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_cs_n_o" LOC = K14;
NET "tdc1_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_err_flag_i" LOC = H16;
NET "tdc1_err_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc1_int_flag_i" LOC = G16;
NET "tdc1_int_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc1_start_dis_o" LOC = F11;
NET "tdc1_start_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc1_stop_dis_o" LOC = E11;
NET "tdc1_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_sdo_i" LOC = L13;
NET "tdc1_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_status_i" LOC = E9;
NET "tdc1_pll_status_i" IOSTANDARD = LVCMOS25;
NET "tdc1_pll_sdi_o" LOC = M13;
NET "tdc1_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "tdc1_start_from_fpga_o" LOC = F9;
NET "tdc1_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[27]" LOC = E17;
NET "tdc1_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[26]" LOC = F17;
NET "tdc1_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[25]" LOC = F18;
NET "tdc1_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[24]" LOC = G18;
NET "tdc1_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[23]" LOC = F20;
NET "tdc1_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[22]" LOC = G20;
NET "tdc1_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[21]" LOC = E21;
NET "tdc1_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[20]" LOC = F21;
NET "tdc1_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[19]" LOC = K21;
NET "tdc1_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[18]" LOC = L21;
NET "tdc1_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[17]" LOC = L20;
NET "tdc1_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[16]" LOC = M20;
NET "tdc1_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[15]" LOC = F22;
NET "tdc1_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[14]" LOC = G22;
NET "tdc1_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[13]" LOC = L19;
NET "tdc1_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[12]" LOC = M19;
NET "tdc1_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[11]" LOC = E23;
NET "tdc1_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[10]" LOC = F23;
NET "tdc1_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[9]" LOC = A25;
NET "tdc1_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[8]" LOC = B25;
NET "tdc1_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[7]" LOC = G21;
NET "tdc1_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[6]" LOC = C24;
NET "tdc1_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[5]" LOC = H21;
NET "tdc1_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[4]" LOC = D24;
NET "tdc1_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[3]" LOC = D25;
NET "tdc1_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[2]" LOC = E25;
NET "tdc1_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[1]" LOC = H22;
NET "tdc1_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "tdc1_data_bus_io[0]" LOC = J22;
NET "tdc1_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[3]" LOC = F14;
NET "tdc1_address_o[3]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[2]" LOC = G14;
NET "tdc1_address_o[2]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[1]" LOC = H14;
NET "tdc1_address_o[1]" IOSTANDARD = LVCMOS25;
NET "tdc1_address_o[0]" LOC = J14;
NET "tdc1_address_o[0]" IOSTANDARD = LVCMOS25;
NET "tdc1_oe_n_o" LOC = G12;
NET "tdc1_oe_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_rd_n_o" LOC = A15;
NET "tdc1_rd_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_wr_n_o" LOC = B15;
NET "tdc1_wr_n_o" IOSTANDARD = LVCMOS25;
NET "tdc1_enable_inputs_o" LOC = J12;
NET "tdc1_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "tdc1_onewire_b" LOC = H12;
NET "tdc1_onewire_b" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_acam_refclk_p_i" LOC = H15;
NET "fmc0_tdc_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "fmc0_tdc_acam_refclk_n_i" LOC = G15;
NET "fmc0_tdc_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "fmc0_tdc_clk_125m_p_i" LOC = E16;
NET "fmc0_tdc_clk_125m_p_i" IOSTANDARD = LVDS_25;
NET "fmc0_tdc_clk_125m_n_i" LOC = D16;
NET "fmc0_tdc_clk_125m_n_i" IOSTANDARD = LVDS_25;
NET "fmc0_tdc_led_trig1_o" LOC = H13;
NET "fmc0_tdc_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_led_trig2_o" LOC = H11;
NET "fmc0_tdc_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_led_trig3_o" LOC = G11;
NET "fmc0_tdc_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_term_en_1_o" LOC = C16;
NET "fmc0_tdc_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_term_en_2_o" LOC = A16;
NET "fmc0_tdc_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_ef1_i" LOC = F19;
NET "fmc0_tdc_ef1_i" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_ef2_i" LOC = E19;
NET "fmc0_tdc_ef2_i" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_term_en_3_o" LOC = F15;
NET "fmc0_tdc_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_term_en_4_o" LOC = E15;
NET "fmc0_tdc_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_term_en_5_o" LOC = F13;
NET "fmc0_tdc_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_led_status_o" LOC = E13;
NET "fmc0_tdc_led_status_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_led_trig4_o" LOC = L11;
NET "fmc0_tdc_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_led_trig5_o" LOC = K11;
NET "fmc0_tdc_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_pll_sclk_o" LOC = M15;
NET "fmc0_tdc_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_pll_dac_sync_o" LOC = K15;
NET "fmc0_tdc_pll_dac_sync_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_pll_cs_n_o" LOC = L14;
NET "fmc0_tdc_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_cs_n_o" LOC = K14;
NET "fmc0_tdc_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_err_flag_i" LOC = H16;
NET "fmc0_tdc_err_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_int_flag_i" LOC = G16;
NET "fmc0_tdc_int_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_start_dis_o" LOC = F11;
NET "fmc0_tdc_start_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_stop_dis_o" LOC = E11;
NET "fmc0_tdc_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_pll_sdo_i" LOC = L13;
NET "fmc0_tdc_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_pll_status_i" LOC = E9;
NET "fmc0_tdc_pll_status_i" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_pll_sdi_o" LOC = M13;
NET "fmc0_tdc_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_start_from_fpga_o" LOC = F9;
NET "fmc0_tdc_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[27]" LOC = E17;
NET "fmc0_tdc_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[26]" LOC = F17;
NET "fmc0_tdc_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[25]" LOC = F18;
NET "fmc0_tdc_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[24]" LOC = G18;
NET "fmc0_tdc_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[23]" LOC = F20;
NET "fmc0_tdc_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[22]" LOC = G20;
NET "fmc0_tdc_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[21]" LOC = E21;
NET "fmc0_tdc_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[20]" LOC = F21;
NET "fmc0_tdc_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[19]" LOC = K21;
NET "fmc0_tdc_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[18]" LOC = L21;
NET "fmc0_tdc_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[17]" LOC = L20;
NET "fmc0_tdc_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[16]" LOC = M20;
NET "fmc0_tdc_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[15]" LOC = F22;
NET "fmc0_tdc_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[14]" LOC = G22;
NET "fmc0_tdc_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[13]" LOC = L19;
NET "fmc0_tdc_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[12]" LOC = M19;
NET "fmc0_tdc_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[11]" LOC = E23;
NET "fmc0_tdc_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[10]" LOC = F23;
NET "fmc0_tdc_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[9]" LOC = A25;
NET "fmc0_tdc_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[8]" LOC = B25;
NET "fmc0_tdc_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[7]" LOC = G21;
NET "fmc0_tdc_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[6]" LOC = C24;
NET "fmc0_tdc_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[5]" LOC = H21;
NET "fmc0_tdc_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[4]" LOC = D24;
NET "fmc0_tdc_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[3]" LOC = D25;
NET "fmc0_tdc_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[2]" LOC = E25;
NET "fmc0_tdc_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[1]" LOC = H22;
NET "fmc0_tdc_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_data_bus_io[0]" LOC = J22;
NET "fmc0_tdc_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_address_o[3]" LOC = F14;
NET "fmc0_tdc_address_o[3]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_address_o[2]" LOC = G14;
NET "fmc0_tdc_address_o[2]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_address_o[1]" LOC = H14;
NET "fmc0_tdc_address_o[1]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_address_o[0]" LOC = J14;
NET "fmc0_tdc_address_o[0]" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_oe_n_o" LOC = G12;
NET "fmc0_tdc_oe_n_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_rd_n_o" LOC = A15;
NET "fmc0_tdc_rd_n_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_wr_n_o" LOC = B15;
NET "fmc0_tdc_wr_n_o" IOSTANDARD = LVCMOS25;
NET "fmc0_tdc_enable_inputs_o" LOC = J12;
NET "fmc0_tdc_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "fmc0_onewire_b" LOC = H12;
NET "fmc0_onewire_b" IOSTANDARD = LVCMOS25;
#----------------------------------------
# FMC2
# FMC1
#----------------------------------------
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 1
NET "tdc2_acam_refclk_p_i" LOC = AF16;
NET "tdc2_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "tdc2_acam_refclk_n_i" LOC = AG16;
NET "tdc2_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "tdc2_125m_clk_p_i" LOC = AH16;
NET "tdc2_125m_clk_p_i" IOSTANDARD = LVDS_25;
NET "tdc2_125m_clk_n_i" LOC = AK16;
NET "tdc2_125m_clk_n_i" IOSTANDARD = LVDS_25;
NET "tdc2_led_trig1_o" LOC = Y20;
NET "tdc2_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig2_o" LOC = W19;
NET "tdc2_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig3_o" LOC = Y19;
NET "tdc2_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_1_o" LOC = AJ17;
NET "tdc2_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_2_o" LOC = AK17;
NET "tdc2_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "tdc2_ef1_i" LOC = AB14;
NET "tdc2_ef1_i" IOSTANDARD = LVCMOS25;
NET "tdc2_ef2_i" LOC = AC14;
NET "tdc2_ef2_i" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_3_o" LOC = AE19;
NET "tdc2_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_4_o" LOC = AF19;
NET "tdc2_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "tdc2_term_en_5_o" LOC = AE24;
NET "tdc2_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_status_o" LOC = AF24;
NET "tdc2_led_status_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig4_o" LOC = Y21;
NET "tdc2_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "tdc2_led_trig5_o" LOC = AA21;
NET "tdc2_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_sclk_o" LOC = AF25;
NET "tdc2_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_dac_sync_n_o" LOC = AG25;
NET "tdc2_pll_dac_sync_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_cs_n_o" LOC = AC19;
NET "tdc2_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_cs_n_o" LOC = AD19;
NET "tdc2_cs_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_err_flag_i" LOC = Y17;
NET "tdc2_err_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc2_int_flag_i" LOC = AA17;
NET "tdc2_int_flag_i" IOSTANDARD = LVCMOS25;
NET "tdc2_start_dis_o" LOC = AB17;
NET "tdc2_start_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc2_stop_dis_o" LOC = AD17;
NET "tdc2_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_sdo_i" LOC = AC20;
NET "tdc2_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_status_i" LOC = AD24;
NET "tdc2_pll_status_i" IOSTANDARD = LVCMOS25;
NET "tdc2_pll_sdi_o" LOC = AB20;
NET "tdc2_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "tdc2_start_from_fpga_o" LOC = AC24;
NET "tdc2_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[27]" LOC = AA15;
NET "tdc2_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[26]" LOC = Y15;
NET "tdc2_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[25]" LOC = AD15;
NET "tdc2_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[24]" LOC = AC15;
NET "tdc2_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[23]" LOC = AB16;
NET "tdc2_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[22]" LOC = Y16;
NET "tdc2_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[21]" LOC = AF15;
NET "tdc2_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[20]" LOC = AE15;
NET "tdc2_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[19]" LOC = AA14;
NET "tdc2_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[18]" LOC = Y14;
NET "tdc2_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[17]" LOC = Y13;
NET "tdc2_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[16]" LOC = W14;
NET "tdc2_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[15]" LOC = AE12;
NET "tdc2_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[14]" LOC = AD12;
NET "tdc2_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[13]" LOC = AF11;
NET "tdc2_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[12]" LOC = AE11;
NET "tdc2_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[11]" LOC = AC12;
NET "tdc2_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[10]" LOC = AB12;
NET "tdc2_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[9]" LOC = AE10;
NET "tdc2_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[8]" LOC = AD10;
NET "tdc2_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[7]" LOC = AH8;
NET "tdc2_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[6]" LOC = AK15;
NET "tdc2_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[5]" LOC = AG8;
NET "tdc2_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[4]" LOC = AJ15;
NET "tdc2_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[3]" LOC = AF13;
NET "tdc2_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[2]" LOC = AE13;
NET "tdc2_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[1]" LOC = AD11;
NET "tdc2_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "tdc2_data_bus_io[0]" LOC = AC11;
NET "tdc2_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[3]" LOC = AF23;
NET "tdc2_address_o[3]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[2]" LOC = AE23;
NET "tdc2_address_o[2]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[1]" LOC = AF21;
NET "tdc2_address_o[1]" IOSTANDARD = LVCMOS25;
NET "tdc2_address_o[0]" LOC = AE21;
NET "tdc2_address_o[0]" IOSTANDARD = LVCMOS25;
NET "tdc2_oe_n_o" LOC = AD22;
NET "tdc2_oe_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_rd_n_o" LOC = AD16;
NET "tdc2_rd_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_wr_n_o" LOC = AC16;
NET "tdc2_wr_n_o" IOSTANDARD = LVCMOS25;
NET "tdc2_enable_inputs_o" LOC = AA19;
NET "tdc2_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "tdc2_onewire_b" LOC = AB19;
NET "tdc2_onewire_b" IOSTANDARD = LVCMOS25;
#----------------------------------------
# SFP slot
#----------------------------------------
NET "clk_125m_gtp_p_i" LOC = B19;
NET "clk_125m_gtp_n_i" LOC = A19;
NET "clk_125m_gtp_n_i" TNM_NET = "clk_125m_gtp_n_i";
TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50 %;
NET "clk_125m_gtp_p_i" TNM_NET = "clk_125m_gtp_p_i";
TIMESPEC TS_clk_125m_gtp_p_i = PERIOD "clk_125m_gtp_p_i" 8 ns HIGH 50 %;
NET "sfp_txp_o" LOC = B23;
NET "sfp_txn_o" LOC = A23;
NET "sfp_rxp_i" LOC = D22;
NET "sfp_rxn_i" LOC = C22;
NET "sfp_los_i" LOC = W25;
NET "sfp_mod_def0_i" LOC = Y26;
NET "sfp_mod_def1_b" LOC = Y27;
NET "sfp_mod_def2_b" LOC = AA24;
#NET "sfp_rate_select_o" LOC = W24;
NET "sfp_tx_disable_o" LOC = AA25;
NET "sfp_tx_fault_i" LOC = AA27;
NET "sfp_los_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
#NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
NET "sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
NET "pll20dac_din_o" LOC = U28;
NET "pll20dac_sclk_o" LOC = AA28;
NET "pll20dac_sync_n_o" LOC = N28;
NET "pll25dac_din_o" LOC = P25;
NET "pll25dac_sclk_o" LOC = N27;
NET "pll25dac_sync_n_o" LOC = P26;
NET "pll20dac_din_o" IOSTANDARD = LVCMOS33;
NET "pll20dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll20dac_sync_n_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_din_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sync_n_o" IOSTANDARD = LVCMOS33;
#----------------------------------------
# UART
#----------------------------------------
NET "uart_txd_o" LOC = U27;
NET "uart_rxd_i" LOC = U25;
NET "uart_txd_o" IOSTANDARD = LVCMOS33;
NET "uart_rxd_i" IOSTANDARD = LVCMOS33;
NET "fmc1_tdc_acam_refclk_p_i" LOC = AF16;
NET "fmc1_tdc_acam_refclk_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_acam_refclk_n_i" LOC = AG16;
NET "fmc1_tdc_acam_refclk_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_clk_125m_p_i" LOC = AH16;
NET "fmc1_tdc_clk_125m_p_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_clk_125m_n_i" LOC = AK16;
NET "fmc1_tdc_clk_125m_n_i" IOSTANDARD = LVDS_25;
NET "fmc1_tdc_led_trig1_o" LOC = Y20;
NET "fmc1_tdc_led_trig1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig2_o" LOC = W19;
NET "fmc1_tdc_led_trig2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig3_o" LOC = Y19;
NET "fmc1_tdc_led_trig3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_1_o" LOC = AJ17;
NET "fmc1_tdc_term_en_1_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_2_o" LOC = AK17;
NET "fmc1_tdc_term_en_2_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef1_i" LOC = AB14;
NET "fmc1_tdc_ef1_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_ef2_i" LOC = AC14;
NET "fmc1_tdc_ef2_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_3_o" LOC = AE19;
NET "fmc1_tdc_term_en_3_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_4_o" LOC = AF19;
NET "fmc1_tdc_term_en_4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_term_en_5_o" LOC = AE24;
NET "fmc1_tdc_term_en_5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_status_o" LOC = AF24;
NET "fmc1_tdc_led_status_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig4_o" LOC = Y21;
NET "fmc1_tdc_led_trig4_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_led_trig5_o" LOC = AA21;
NET "fmc1_tdc_led_trig5_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sclk_o" LOC = AF25;
NET "fmc1_tdc_pll_sclk_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_dac_sync_o" LOC = AG25;
NET "fmc1_tdc_pll_dac_sync_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_cs_n_o" LOC = AC19;
NET "fmc1_tdc_pll_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_cs_n_o" LOC = AD19;
NET "fmc1_tdc_cs_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_err_flag_i" LOC = Y17;
NET "fmc1_tdc_err_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_int_flag_i" LOC = AA17;
NET "fmc1_tdc_int_flag_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_dis_o" LOC = AB17;
NET "fmc1_tdc_start_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_stop_dis_o" LOC = AD17;
NET "fmc1_tdc_stop_dis_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdo_i" LOC = AC20;
NET "fmc1_tdc_pll_sdo_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_status_i" LOC = AD24;
NET "fmc1_tdc_pll_status_i" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_pll_sdi_o" LOC = AB20;
NET "fmc1_tdc_pll_sdi_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_start_from_fpga_o" LOC = AC24;
NET "fmc1_tdc_start_from_fpga_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[27]" LOC = AA15;
NET "fmc1_tdc_data_bus_io[27]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[26]" LOC = Y15;
NET "fmc1_tdc_data_bus_io[26]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[25]" LOC = AD15;
NET "fmc1_tdc_data_bus_io[25]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[24]" LOC = AC15;
NET "fmc1_tdc_data_bus_io[24]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[23]" LOC = AB16;
NET "fmc1_tdc_data_bus_io[23]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[22]" LOC = Y16;
NET "fmc1_tdc_data_bus_io[22]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[21]" LOC = AF15;
NET "fmc1_tdc_data_bus_io[21]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[20]" LOC = AE15;
NET "fmc1_tdc_data_bus_io[20]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[19]" LOC = AA14;
NET "fmc1_tdc_data_bus_io[19]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[18]" LOC = Y14;
NET "fmc1_tdc_data_bus_io[18]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[17]" LOC = Y13;
NET "fmc1_tdc_data_bus_io[17]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[16]" LOC = W14;
NET "fmc1_tdc_data_bus_io[16]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[15]" LOC = AE12;
NET "fmc1_tdc_data_bus_io[15]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[14]" LOC = AD12;
NET "fmc1_tdc_data_bus_io[14]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[13]" LOC = AF11;
NET "fmc1_tdc_data_bus_io[13]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[12]" LOC = AE11;
NET "fmc1_tdc_data_bus_io[12]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[11]" LOC = AC12;
NET "fmc1_tdc_data_bus_io[11]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[10]" LOC = AB12;
NET "fmc1_tdc_data_bus_io[10]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[9]" LOC = AE10;
NET "fmc1_tdc_data_bus_io[9]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[8]" LOC = AD10;
NET "fmc1_tdc_data_bus_io[8]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[7]" LOC = AH8;
NET "fmc1_tdc_data_bus_io[7]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[6]" LOC = AK15;
NET "fmc1_tdc_data_bus_io[6]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[5]" LOC = AG8;
NET "fmc1_tdc_data_bus_io[5]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[4]" LOC = AJ15;
NET "fmc1_tdc_data_bus_io[4]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[3]" LOC = AF13;
NET "fmc1_tdc_data_bus_io[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[2]" LOC = AE13;
NET "fmc1_tdc_data_bus_io[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[1]" LOC = AD11;
NET "fmc1_tdc_data_bus_io[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_data_bus_io[0]" LOC = AC11;
NET "fmc1_tdc_data_bus_io[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[3]" LOC = AF23;
NET "fmc1_tdc_address_o[3]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[2]" LOC = AE23;
NET "fmc1_tdc_address_o[2]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[1]" LOC = AF21;
NET "fmc1_tdc_address_o[1]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_address_o[0]" LOC = AE21;
NET "fmc1_tdc_address_o[0]" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_oe_n_o" LOC = AD22;
NET "fmc1_tdc_oe_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_rd_n_o" LOC = AD16;
NET "fmc1_tdc_rd_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_wr_n_o" LOC = AC16;
NET "fmc1_tdc_wr_n_o" IOSTANDARD = LVCMOS25;
NET "fmc1_tdc_enable_inputs_o" LOC = AA19;
NET "fmc1_tdc_enable_inputs_o" IOSTANDARD = LVCMOS25;
NET "fmc1_onewire_b" LOC = AB19;
NET "fmc1_onewire_b" IOSTANDARD = LVCMOS25;
#----------------------------------------
# Clock stuff
#----------------------------------------
# SVEC VCXO clock/reset
NET "clk_20m_vcxo_i" LOC = V26;
NET "por_n_i" LOC = AD28;
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
NET "por_n_i" IOSTANDARD = LVCMOS33;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
# 62.5MHz Xilinx PLL clock/reset
NET "clk_sys_62m5" TNM_NET = "clk_sys_62m5";
NET "fp_gpio3_b" TNM_NET = fp_gpio3;
TIMESPEC TS_fp_gpio3 = PERIOD "fp_gpio3" 100 ns HIGH 50%;
# 125MHz PLL ref
NET "clk_125m_pllref_n_i" LOC = AB30;
NET "clk_125m_pllref_p_i" LOC = AB28;
# 125MHz TDC PLL clock
NET "tdc1_125m_clk" TNM_NET = "tdc1_125m_clk";
NET "tdc2_125m_clk" TNM_NET = "tdc2_125m_clk";
NET "fmc0_tdc_clk_125m" TNM_NET = "fmc0_tdc_clk_125m";
NET "fmc1_tdc_clk_125m" TNM_NET = "fmc1_tdc_clk_125m";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2013/07/19
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50 %;
NET "fmc0_tdc_clk_125m_n_i" TNM_NET = "fmc0_tdc_clk_125m_n_i";
TIMESPEC TS_fmc0_tdc_tdc_125m_clk_n_i = PERIOD "fmc0_tdc_clk_125m_n_i" 8 ns HIGH 50 %;
NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50 %;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50 %;
NET "fmc0_tdc_clk_125m_p_i" TNM_NET = "fmc0_tdc_clk_125m_p_i";
TIMESPEC TS_fmc0_tdc_clk_125m_p_i = PERIOD "fmc0_tdc_clk_125m_p_i" 8 ns HIGH 50 %;
NET "tdc1_125m_clk_n_i" TNM_NET = "tdc1_125m_clk_n_i";
TIMESPEC TS_tdc1_tdc_125m_clk_n_i = PERIOD "tdc1_125m_clk_n_i" 8 ns HIGH 50 %;
NET "tdc1_125m_clk_p_i" TNM_NET = "tdc1_125m_clk_p_i";
TIMESPEC TS_tdc1_125m_clk_p_i = PERIOD "tdc1_125m_clk_p_i" 8 ns HIGH 50 %;
NET "fmc1_tdc_clk_125m_p_i" TNM_NET = "fmc1_tdc_clk_125m_p_i";
TIMESPEC TS_fmc1_tdc_tdc_125m_clk_p_i = PERIOD "fmc1_tdc_clk_125m_p_i" 8 ns HIGH 50 %;
NET "tdc2_125m_clk_p_i" TNM_NET = "tdc2_125m_clk_p_i";
TIMESPEC TS_tdc2_tdc_125m_clk_p_i = PERIOD "tdc2_125m_clk_p_i" 8 ns HIGH 50 %;
NET "tdc2_125m_clk_n_i" TNM_NET = "tdc2_125m_clk_n_i";
TIMESPEC TS_tdc2_tdc_125m_clk_n_i = PERIOD "tdc2_125m_clk_n_i" 8 ns HIGH 50 %;
NET "fmc1_tdc_clk_125m_n_i" TNM_NET = "fmc1_tdc_clk_125m_n_i";
TIMESPEC TS_fmc1_tdc_tdc_125m_clk_n_i = PERIOD "fmc1_tdc_clk_125m_n_i" 8 ns HIGH 50 %;
# TS_IGNORE
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "fmc0_tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock2 = FROM "fmc0_tdc_clk_125m" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "fmc1_tdc_clk_125m" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "fmc1_tdc_clk_125m" TO "clk_sys_62m5" 20ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_sys_62m5" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_sys_62m5" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
TIMESPEC ts_ignore_xclock4 = FROM "clk_sys_62m5" TO "clk_20m_vcxo_i" 200 ns DATAPATHONLY;
#TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50 %;
#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2017/12/06
NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
#NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
#TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PlanAhead Generated miscellaneous constraints
NET "tdc1_address_o[3]" SLEW = FAST;
NET "tdc1_address_o[2]" SLEW = FAST;
NET "tdc1_address_o[1]" SLEW = FAST;
NET "tdc1_address_o[0]" SLEW = FAST;
NET "tdc1_data_bus_io[27]" SLEW = FAST;
NET "tdc1_data_bus_io[26]" SLEW = FAST;
NET "tdc1_data_bus_io[25]" SLEW = FAST;
NET "tdc1_data_bus_io[24]" SLEW = FAST;
NET "tdc1_data_bus_io[23]" SLEW = FAST;
NET "tdc1_data_bus_io[22]" SLEW = FAST;
NET "tdc1_data_bus_io[21]" SLEW = FAST;
NET "tdc1_data_bus_io[20]" SLEW = FAST;
NET "tdc1_data_bus_io[19]" SLEW = FAST;
NET "tdc1_data_bus_io[18]" SLEW = FAST;
NET "tdc1_data_bus_io[17]" SLEW = FAST;
NET "tdc1_data_bus_io[16]" SLEW = FAST;
NET "tdc1_data_bus_io[15]" SLEW = FAST;
NET "tdc1_data_bus_io[14]" SLEW = FAST;
NET "tdc1_data_bus_io[13]" SLEW = FAST;
NET "tdc1_data_bus_io[12]" SLEW = FAST;
NET "tdc1_data_bus_io[11]" SLEW = FAST;
NET "tdc1_data_bus_io[10]" SLEW = FAST;
NET "tdc1_data_bus_io[9]" SLEW = FAST;
NET "tdc1_data_bus_io[8]" SLEW = FAST;
NET "tdc1_data_bus_io[7]" SLEW = FAST;
NET "tdc1_data_bus_io[6]" SLEW = FAST;
NET "tdc1_data_bus_io[5]" SLEW = FAST;
NET "tdc1_data_bus_io[4]" SLEW = FAST;
NET "tdc1_data_bus_io[3]" SLEW = FAST;
NET "tdc1_data_bus_io[2]" SLEW = FAST;
NET "tdc1_data_bus_io[1]" SLEW = FAST;
NET "tdc1_data_bus_io[0]" SLEW = FAST;
NET "tdc2_address_o[3]" SLEW = FAST;
NET "tdc2_address_o[2]" SLEW = FAST;
NET "tdc2_address_o[1]" SLEW = FAST;
NET "tdc2_address_o[0]" SLEW = FAST;
NET "tdc2_data_bus_io[27]" SLEW = FAST;
NET "tdc2_data_bus_io[26]" SLEW = FAST;
NET "tdc2_data_bus_io[25]" SLEW = FAST;
NET "tdc2_data_bus_io[24]" SLEW = FAST;
NET "tdc2_data_bus_io[23]" SLEW = FAST;
NET "tdc2_data_bus_io[22]" SLEW = FAST;
NET "tdc2_data_bus_io[21]" SLEW = FAST;
NET "tdc2_data_bus_io[20]" SLEW = FAST;
NET "tdc2_data_bus_io[19]" SLEW = FAST;
NET "tdc2_data_bus_io[18]" SLEW = FAST;
NET "tdc2_data_bus_io[17]" SLEW = FAST;
NET "tdc2_data_bus_io[16]" SLEW = FAST;
NET "tdc2_data_bus_io[15]" SLEW = FAST;
NET "tdc2_data_bus_io[14]" SLEW = FAST;
NET "tdc2_data_bus_io[13]" SLEW = FAST;
NET "tdc2_data_bus_io[12]" SLEW = FAST;
NET "tdc2_data_bus_io[11]" SLEW = FAST;
NET "tdc2_data_bus_io[10]" SLEW = FAST;
NET "tdc2_data_bus_io[9]" SLEW = FAST;
NET "tdc2_data_bus_io[8]" SLEW = FAST;
NET "tdc2_data_bus_io[7]" SLEW = FAST;
NET "tdc2_data_bus_io[6]" SLEW = FAST;
NET "tdc2_data_bus_io[5]" SLEW = FAST;
NET "tdc2_data_bus_io[4]" SLEW = FAST;
NET "tdc2_data_bus_io[3]" SLEW = FAST;
NET "tdc2_data_bus_io[2]" SLEW = FAST;
NET "tdc2_data_bus_io[1]" SLEW = FAST;
NET "tdc2_data_bus_io[0]" SLEW = FAST;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# PlanAhead Generated miscellaneous constraints
NET "fmc0_tdc_address_o[3]" SLEW = FAST;
NET "fmc0_tdc_address_o[2]" SLEW = FAST;
NET "fmc0_tdc_address_o[1]" SLEW = FAST;
NET "fmc0_tdc_address_o[0]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[27]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[26]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[25]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[24]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[23]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[22]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[21]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[20]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[19]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[18]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[17]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[16]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[15]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[14]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[13]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[12]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[11]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[10]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[9]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[8]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[7]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[6]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[5]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[4]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[3]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[2]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[1]" SLEW = FAST;
NET "fmc0_tdc_data_bus_io[0]" SLEW = FAST;
NET "fmc1_tdc_address_o[3]" SLEW = FAST;
NET "fmc1_tdc_address_o[2]" SLEW = FAST;
NET "fmc1_tdc_address_o[1]" SLEW = FAST;
NET "fmc1_tdc_address_o[0]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[27]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[26]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[25]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[24]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[23]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[22]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[21]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[20]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[19]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[18]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[17]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[16]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[15]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[14]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[13]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[12]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[11]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[10]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[9]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[8]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[7]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[6]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[5]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[4]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[3]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[2]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[1]" SLEW = FAST;
NET "fmc1_tdc_data_bus_io[0]" SLEW = FAST;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
#TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
# Force PPS output to always be placed as IOB register
INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
# External async reset
NET "por_n_i" TIG;
NET "vme_rst_n_i" TIG;
hdl/top/svec/wr_svec_tdc.vhd
View file @ 182ada36
......@@ -83,20 +83,6 @@
-- | |___________________LEDs_______________________| | |
-- | | |
-- |__________________________________________________________________| |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Grzegorz Daniluk (Grzegorz.Daniluk@cern.ch)
-- Date 05/2014 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 08/2013 v1 EG design for SVEC; two cores; synchronizer between vme and the cores |
-- 05/2014 v2 EG added White Rabbit |
-- 12/2017 v7 GD Top file reorganized to benefit from WRPC Board wrapper.
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -128,17 +114,22 @@ use work.wr_svec_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.synthesis_descriptor.all;
--=================================================================================================
-- Entity declaration for top_tdc
--=================================================================================================
entity wr_svec_tdc is
generic (
g_simulation : boolean := false);
generic
(g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
g_USE_FIFO_READOUT : boolean := TRUE;
g_USE_DMA_READOUT : boolean := FALSE;
g_SIMULATION : integer := 0;
g_USE_FAKE_TIMESTAMPS_FOR_SIM : boolean := FALSE -- when instantiated in a test-bench
);
port (
-- VCXO clock, PoR
por_n_i : in std_logic; -- PoR
rst_n_i : in std_logic; -- Reset from system fpga
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
-- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
......@@ -154,7 +145,7 @@ entity wr_svec_tdc is
sfp_mod_def0_i : in std_logic; -- SFP detect pin
sfp_mod_def1_b : inout std_logic; -- SFP scl
sfp_mod_def2_b : inout std_logic; -- SFP sda
sfp_rate_select_b : inout std_logic := '0';
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
......@@ -169,33 +160,41 @@ entity wr_svec_tdc is
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
-- 1-wire
carrier_onewire_b : inout std_logic;
onewire_b : inout std_logic;
-- SPI Flash
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-- I2C EEPROM
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
-- SVEC PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
pcbrev_i : in std_logic_vector(4 downto 0);
-- Mezzanines presence
tdc1_prsntm2c_n_i : in std_logic; -- Presence of mezzanine #1
tdc2_prsntm2c_n_i : in std_logic; -- Presence of mezzanine #2
fmc0_prsnt_m2c_n_i : in std_logic; -- Presence of mezzanine #1
fmc1_prsnt_m2c_n_i : in std_logic; -- Presence of mezzanine #2
-- SVEC Front panel LEDs
fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0);
-- SVEC Front panel LEMOs
fp_gpio1_o : out std_logic; -- PPS output
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
-- SVEC Front panel LEDs and LEMOs
fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_b : out std_logic; -- Ref clock div2 output
fp_gpio3_b : in std_logic; -- ext 10MHz clock input
fp_gpio4_b : in std_logic; -- ext PPS input
fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic;
fp_gpio34_a2b_o : out std_logic;
-- VME interface
vme_as_n_i : in std_logic;
vme_rst_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_write_n_i : in std_logic;
vme_am_i : in std_logic_vector(5 downto 0);
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_ga_i : in std_logic_vector(5 downto 0);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_berr_o : inout std_logic;
vme_dtack_n_o : inout std_logic;
vme_retry_n_o : out std_logic;
......@@ -203,8 +202,8 @@ entity wr_svec_tdc is
vme_lword_n_b : inout std_logic;
vme_addr_b : inout std_logic_vector(31 downto 1);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_bbsy_n_i : in std_logic;
vme_irq_o : out std_logic_vector(6 downto 0);
vme_gap_i : in std_logic;
vme_irq_o : out std_logic_vector(7 downto 1);
vme_iack_n_i : in std_logic;
vme_iackin_n_i : in std_logic;
vme_iackout_n_o : out std_logic;
......@@ -216,109 +215,109 @@ entity wr_svec_tdc is
-- TDC mezzanine board on FMC slot 1
-- TDC1 PLL AD9516 and DAC AD5662 interface
tdc1_pll_sclk_o : out std_logic;
tdc1_pll_sdi_o : out std_logic;
tdc1_pll_cs_n_o : out std_logic;
tdc1_pll_dac_sync_n_o : out std_logic;
tdc1_pll_sdo_i : in std_logic;
tdc1_pll_status_i : in std_logic;
tdc1_125m_clk_p_i : in std_logic;
tdc1_125m_clk_n_i : in std_logic;
tdc1_acam_refclk_p_i : in std_logic;
tdc1_acam_refclk_n_i : in std_logic;
fmc0_tdc_pll_sclk_o : out std_logic;
fmc0_tdc_pll_sdi_o : out std_logic;
fmc0_tdc_pll_cs_n_o : out std_logic;
fmc0_tdc_pll_dac_sync_o : out std_logic;
fmc0_tdc_pll_sdo_i : in std_logic;
fmc0_tdc_pll_status_i : in std_logic;
fmc0_tdc_clk_125m_p_i : in std_logic;
fmc0_tdc_clk_125m_n_i : in std_logic;
fmc0_tdc_acam_refclk_p_i : in std_logic;
fmc0_tdc_acam_refclk_n_i : in std_logic;
-- TDC1 ACAM timing interface
tdc1_start_from_fpga_o : out std_logic;
tdc1_err_flag_i : in std_logic;
tdc1_int_flag_i : in std_logic;
tdc1_start_dis_o : out std_logic;
tdc1_stop_dis_o : out std_logic;
fmc0_tdc_start_from_fpga_o : out std_logic;
fmc0_tdc_err_flag_i : in std_logic;
fmc0_tdc_int_flag_i : in std_logic;
fmc0_tdc_start_dis_o : out std_logic;
fmc0_tdc_stop_dis_o : out std_logic;
-- TDC1 ACAM data interface
tdc1_data_bus_io : inout std_logic_vector(27 downto 0);
tdc1_address_o : out std_logic_vector(3 downto 0);
tdc1_cs_n_o : out std_logic;
tdc1_oe_n_o : out std_logic;
tdc1_rd_n_o : out std_logic;
tdc1_wr_n_o : out std_logic;
tdc1_ef1_i : in std_logic;
tdc1_ef2_i : in std_logic;
fmc0_tdc_data_bus_io : inout std_logic_vector(27 downto 0);
fmc0_tdc_address_o : out std_logic_vector(3 downto 0);
fmc0_tdc_cs_n_o : out std_logic;
fmc0_tdc_oe_n_o : out std_logic;
fmc0_tdc_rd_n_o : out std_logic;
fmc0_tdc_wr_n_o : out std_logic;
fmc0_tdc_ef1_i : in std_logic;
fmc0_tdc_ef2_i : in std_logic;
-- TDC1 Input Logic
tdc1_enable_inputs_o : out std_logic;
tdc1_term_en_1_o : out std_logic;
tdc1_term_en_2_o : out std_logic;
tdc1_term_en_3_o : out std_logic;
tdc1_term_en_4_o : out std_logic;
tdc1_term_en_5_o : out std_logic;
fmc0_tdc_enable_inputs_o : out std_logic;
fmc0_tdc_term_en_1_o : out std_logic;
fmc0_tdc_term_en_2_o : out std_logic;
fmc0_tdc_term_en_3_o : out std_logic;
fmc0_tdc_term_en_4_o : out std_logic;
fmc0_tdc_term_en_5_o : out std_logic;
-- TDC1 1-wire UniqueID & Thermometer
tdc1_onewire_b : inout std_logic;
fmc0_onewire_b : inout std_logic;
-- TDC1 EEPROM I2C
tdc1_scl_b : inout std_logic;
tdc1_sda_b : inout std_logic;
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- TDC1 LEDs
tdc1_led_status_o : out std_logic;
tdc1_led_trig1_o : out std_logic;
tdc1_led_trig2_o : out std_logic;
tdc1_led_trig3_o : out std_logic;
tdc1_led_trig4_o : out std_logic;
tdc1_led_trig5_o : out std_logic;
fmc0_tdc_led_status_o : out std_logic;
fmc0_tdc_led_trig1_o : out std_logic;
fmc0_tdc_led_trig2_o : out std_logic;
fmc0_tdc_led_trig3_o : out std_logic;
fmc0_tdc_led_trig4_o : out std_logic;
fmc0_tdc_led_trig5_o : out std_logic;
-- TDC1 Input channels, also arriving to the FPGA (not used for the moment)
tdc1_in_fpga_1_i : in std_logic;
tdc1_in_fpga_2_i : in std_logic;
tdc1_in_fpga_3_i : in std_logic;
tdc1_in_fpga_4_i : in std_logic;
tdc1_in_fpga_5_i : in std_logic;
fmc0_tdc_in_fpga_1_i : in std_logic;
fmc0_tdc_in_fpga_2_i : in std_logic;
fmc0_tdc_in_fpga_3_i : in std_logic;
fmc0_tdc_in_fpga_4_i : in std_logic;
fmc0_tdc_in_fpga_5_i : in std_logic;
-- TDC mezzanine board on FMC slot 2
-- TDC2 PLL AD9516 and DAC AD5662 interface
tdc2_pll_sclk_o : out std_logic;
tdc2_pll_sdi_o : out std_logic;
tdc2_pll_cs_n_o : out std_logic;
tdc2_pll_dac_sync_n_o : out std_logic;
tdc2_pll_sdo_i : in std_logic;
tdc2_pll_status_i : in std_logic;
tdc2_125m_clk_p_i : in std_logic;
tdc2_125m_clk_n_i : in std_logic;
tdc2_acam_refclk_p_i : in std_logic;
tdc2_acam_refclk_n_i : in std_logic;
fmc1_tdc_pll_sclk_o : out std_logic;
fmc1_tdc_pll_sdi_o : out std_logic;
fmc1_tdc_pll_cs_n_o : out std_logic;
fmc1_tdc_pll_dac_sync_o : out std_logic;
fmc1_tdc_pll_sdo_i : in std_logic;
fmc1_tdc_pll_status_i : in std_logic;
fmc1_tdc_clk_125m_p_i : in std_logic;
fmc1_tdc_clk_125m_n_i : in std_logic;
fmc1_tdc_acam_refclk_p_i : in std_logic;
fmc1_tdc_acam_refclk_n_i : in std_logic;
-- TDC2 ACAM timing interface
tdc2_start_from_fpga_o : out std_logic;
tdc2_err_flag_i : in std_logic;
tdc2_int_flag_i : in std_logic;
tdc2_start_dis_o : out std_logic;
tdc2_stop_dis_o : out std_logic;
fmc1_tdc_start_from_fpga_o : out std_logic;
fmc1_tdc_err_flag_i : in std_logic;
fmc1_tdc_int_flag_i : in std_logic;
fmc1_tdc_start_dis_o : out std_logic;
fmc1_tdc_stop_dis_o : out std_logic;
-- TDC2 ACAM data interface
tdc2_data_bus_io : inout std_logic_vector(27 downto 0);
tdc2_address_o : out std_logic_vector(3 downto 0);
tdc2_cs_n_o : out std_logic;
tdc2_oe_n_o : out std_logic;
tdc2_rd_n_o : out std_logic;
tdc2_wr_n_o : out std_logic;
tdc2_ef1_i : in std_logic;
tdc2_ef2_i : in std_logic;
fmc1_tdc_data_bus_io : inout std_logic_vector(27 downto 0);
fmc1_tdc_address_o : out std_logic_vector(3 downto 0);
fmc1_tdc_cs_n_o : out std_logic;
fmc1_tdc_oe_n_o : out std_logic;
fmc1_tdc_rd_n_o : out std_logic;
fmc1_tdc_wr_n_o : out std_logic;
fmc1_tdc_ef1_i : in std_logic;
fmc1_tdc_ef2_i : in std_logic;
-- TDC2 Input Logic
tdc2_enable_inputs_o : out std_logic;
tdc2_term_en_1_o : out std_logic;
tdc2_term_en_2_o : out std_logic;
tdc2_term_en_3_o : out std_logic;
tdc2_term_en_4_o : out std_logic;
tdc2_term_en_5_o : out std_logic;
fmc1_tdc_enable_inputs_o : out std_logic;
fmc1_tdc_term_en_1_o : out std_logic;
fmc1_tdc_term_en_2_o : out std_logic;
fmc1_tdc_term_en_3_o : out std_logic;
fmc1_tdc_term_en_4_o : out std_logic;
fmc1_tdc_term_en_5_o : out std_logic;
-- TDC2 1-wire UniqueID & Thermometer
tdc2_onewire_b : inout std_logic;
fmc1_onewire_b : inout std_logic;
-- TDC2 EEPROM I2C
tdc2_scl_b : inout std_logic;
tdc2_sda_b : inout std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic;
-- TDC2 LEDs
tdc2_led_status_o : out std_logic;
tdc2_led_trig1_o : out std_logic;
tdc2_led_trig2_o : out std_logic;
tdc2_led_trig3_o : out std_logic;
tdc2_led_trig4_o : out std_logic;
tdc2_led_trig5_o : out std_logic;
fmc1_tdc_led_status_o : out std_logic;
fmc1_tdc_led_trig1_o : out std_logic;
fmc1_tdc_led_trig2_o : out std_logic;
fmc1_tdc_led_trig3_o : out std_logic;
fmc1_tdc_led_trig4_o : out std_logic;
fmc1_tdc_led_trig5_o : out std_logic;
-- TDC2 Input channels, also arriving to the FPGA (not used for the moment)
tdc2_in_fpga_1_i : in std_logic;
tdc2_in_fpga_2_i : in std_logic;
tdc2_in_fpga_3_i : in std_logic;
tdc2_in_fpga_4_i : in std_logic;
tdc2_in_fpga_5_i : in std_logic);
fmc1_tdc_in_fpga_1_i : in std_logic;
fmc1_tdc_in_fpga_2_i : in std_logic;
fmc1_tdc_in_fpga_3_i : in std_logic;
fmc1_tdc_in_fpga_4_i : in std_logic;
fmc1_tdc_in_fpga_5_i : in std_logic);
end wr_svec_tdc;
--=================================================================================================
......@@ -326,135 +325,96 @@ end wr_svec_tdc;
--=================================================================================================
architecture rtl of wr_svec_tdc is
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
-- Number of masters attached to the primary wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 1;
constant c_SVEC_INFO_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000001F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
version => x"00000001",
date => x"20121116",
name => "WB-SVEC.CSR ")));
-- Constant regarding the Carrier type
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := x"0002";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Constants regarding the SDB crossbar
constant c_NUM_WB_SLAVES : integer := 1;
constant c_NUM_WB_MASTERS : integer := 5;
constant c_MASTER_VME : integer := 0;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant c_SLAVE_SVEC_INFO : integer := 0; -- SVEC carrier info
constant c_SLAVE_VIC : integer := 1; -- Vector Interrupt controller
constant c_SLAVE_TDC0 : integer := 2; -- TDC mezzanine #1
constant c_SLAVE_TDC1 : integer := 3; -- TDC mezzanine #2
constant c_SLAVE_WRCORE : integer := 4; -- White Rabbit PTP core
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_FMC_TDC1_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_FMC_TDC2_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(0 => f_sdb_embed_device (c_SVEC_INFO_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00002000"),
2 => f_sdb_embed_bridge (c_FMC_TDC1_SDB_BRIDGE, x"00010000"),
3 => f_sdb_embed_bridge (c_FMC_TDC2_SDB_BRIDGE, x"00020000"),
4 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00040000"),
5 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
6 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
-- Number of slaves attached to the primary wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 3;
constant c_WB_SLAVE_METADATA : integer := 0;
constant c_WB_SLAVE_FMC0_TDC : integer := 1; -- FMC slot 1 TDC mezzanine
constant c_WB_SLAVE_FMC1_TDC : integer := 2; -- FMC slot 2 TDC mezzanine
-- Primary Wishbone master(s) offsets
constant c_WB_MASTER_VME : integer := 0;
-- Convention metadata base address
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
constant c_WB_LAYOUT_ADDR :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => c_METADATA_ADDR,
c_WB_SLAVE_FMC0_TDC => x"0001_0000",
c_WB_SLAVE_FMC1_TDC => x"0002_0000");
-- mask is 18 bits long and is active-low
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes: not(0x40 -1) = not(0x3F) = c0
c_WB_SLAVE_FMC0_TDC => x"0003_0000", -- 0x10000 bytes
c_WB_SLAVE_FMC1_TDC => x"0003_0000");
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00013000",
1 => x"00023000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
signal areset_n : std_logic;
-- Clocks
-- Clocks/ reset
-- CLOCK DOMAIN: 62.5 MHz system clock derived from clk_20m_vcxo_i by a Xilinx PLL: clk_62m5_sys
signal clk_sys_62m5 : std_logic;
signal clk_sys_62m5 : std_logic;
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1 and TDC2
signal tdc1_125m_clk : std_logic;
signal tdc2_125m_clk : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal fmc0_tdc_clk_125m : std_logic;
signal fmc1_tdc_clk_125m : std_logic;
signal areset_n : std_logic;
---------------------------------------------------------------------------------------------------
-- Resets
-- system reset, synched with 62.5 MHz clock,driven by the VME reset and power-up reset pins.
signal rst_sys_62m5_n : std_logic;
signal rst_sys_62m5_n : std_logic;
-- reset input to the clks_rsts_manager units of the two TDC cores;
-- this reset initiates the configuration of the mezzanines PLL
signal tdc1_soft_rst_n : std_logic; -- driven by carrier CSR reserved bit 0
signal tdc2_soft_rst_n : std_logic; -- driven by carrier CSR reserved bit 1
signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
---------------------------------------------------------------------------------------------------
-- VME interface
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(6 downto 0);
---------------------------------------------------------------------------------------------------
-- White Rabbit signals to TDC mezzanine
-- White Rabbit signals to TDC mezzanines
signal tm_link_up, tm_time_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_clk_aux_lock_en, tm_clk_aux_locked: std_logic_vector(1 downto 0);
signal pps, pps_led : std_logic;
-- White Rabbit signals to clks_rsts_manager
signal tm_dac_value : std_logic_vector(23 downto 0);
signal tm_dac_wr_p : std_logic_vector(1 downto 0);
-- White Rabbit to SFP EEPROM
signal sfp_scl_out, sfp_scl_in : std_logic;
signal sfp_sda_out, sfp_sda_in : std_logic;
-- White Rabbit Carrier 1-Wire
signal wrc_owr_oe, wrc_owr_data : std_logic;
---------------------------------------------------------------------------------------------------
-- Crossbar
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array (c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
signal vme_wb_in : t_wishbone_master_in;
signal cnx_slave_out : t_wishbone_slave_out_array (c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array (c_NUM_WB_SLAVES-1 downto 0);
---------------------------------------------------------------------------------------------------
-- Interrupts
signal irq_to_vmecore : std_logic;
signal tdc1_irq, tdc2_irq : std_logic;
signal irq_vector : std_logic_vector(1 downto 0);
---------------------------------------------------------------------------------------------------
-- Mezzanines EEPROM
signal tdc1_scl_oen, tdc1_scl_in : std_logic;
signal tdc1_sda_oen, tdc1_sda_in : std_logic;
signal tdc2_scl_oen, tdc2_scl_in : std_logic;
signal tdc2_sda_oen, tdc2_sda_in : std_logic;
signal fmc0_scl_oen, fmc0_scl_in : std_logic;
signal fmc0_sda_oen, fmc0_sda_in : std_logic;
signal fmc1_scl_oen, fmc1_scl_in : std_logic;
signal fmc1_sda_oen, fmc1_sda_in : std_logic;
-- LEDs
signal led_state : std_logic_vector(15 downto 0);
signal tdc1_ef, tdc2_ef, led_tdc1_ef : std_logic;
signal led_tdc2_ef, led_vme_access : std_logic;
signal fmc0_tdc_ef, fmc1_tdc_ef : std_logic;
signal led_fmc0_tdc_ef, led_fmc1_tdc_ef : std_logic;
signal led_vme_access : std_logic;
signal wr_led_act, wr_led_link : std_logic;
--=================================================================================================
......@@ -463,92 +423,161 @@ architecture rtl of wr_svec_tdc is
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
areset_n <= vme_rst_n_i and por_n_i;
tdc1_soft_rst_n <= carrier_info_fmc_rst(0) and rst_sys_62m5_n;
tdc2_soft_rst_n <= carrier_info_fmc_rst(1) and rst_sys_62m5_n;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Tristates for mezzanine EEPROM
tdc2_scl_b <= '0' when (tdc2_scl_oen = '0') else 'Z';
tdc2_sda_b <= '0' when (tdc2_sda_oen = '0') else 'Z';
areset_n <= vme_sysreset_n_i and rst_n_i;
---------------------------------------------------------------------------------------------------
-- SVEC Board Wrapper --
-- SVEC Board Base --
---------------------------------------------------------------------------------------------------
cmp_xwrc_board_svec : xwrc_board_svec
inst_svec_base : entity work.svec_base_wr
generic map (
g_simulation => f_bool2int(g_simulation),
g_with_external_clock_input => FALSE,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_fabric_iface => plain,
g_aux_clks => 2)
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_WR => TRUE,
g_WITH_DDR4 => FALSE,
g_WITH_DDR5 => FALSE,
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 2,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 2,
g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION)
port map (
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i(0) => tdc1_125m_clk,
clk_aux_i(1) => tdc2_125m_clk,
areset_n_i => areset_n,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_b,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
onewire_i => wrc_owr_data,
onewire_oen_o => wrc_owr_oe,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
wb_slave_o => cnx_master_in(c_SLAVE_WRCORE),
wb_slave_i => cnx_master_out(c_SLAVE_WRCORE),
tm_link_up_o => tm_link_up,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr_p,
tm_clk_aux_lock_en_i=> tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
pps_p_o => fp_gpio1_o,
led_link_o => wr_led_link,
led_act_o => wr_led_act);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for 1-wire thermometer
carrier_onewire_b <= '0' when wrc_owr_oe = '1' else 'Z';
wrc_owr_data <= carrier_onewire_b;
---------------------------------------------------------
-- Clocks/ Resets
---------------------------------------------------------
rst_n_i => areset_n,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i(0) => fmc0_tdc_clk_125m,
clk_aux_i(1) => fmc1_tdc_clk_125m,
clk_10m_ext_i => '0',
pps_ext_i => '0',
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => open,
---------------------------------------------------------
-- VME interface
---------------------------------------------------------
vme_write_n_i => vme_write_n_i,
vme_sysreset_n_i => vme_sysreset_n_i,
vme_retry_oe_o => vme_retry_oe_o,
vme_retry_n_o => vme_retry_n_o,
vme_lword_n_b => vme_lword_n_b,
vme_iackout_n_o => vme_iackout_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_gap_i => vme_gap_i,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_ds_n_i => vme_ds_n_i,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
vme_as_n_i => vme_as_n_i,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
vme_irq_o => vme_irq_o,
vme_ga_i => vme_ga_i,
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
---------------------------------------------------------
-- DDR - not used
---------------------------------------------------------
ddr4_clk_i => '0',
ddr4_rst_n_i => '1',
ddr5_clk_i => '0',
ddr5_rst_n_i => '1',
---------------------------------------------------------
-- Carrier peripherals
---------------------------------------------------------
-- 1-wire
onewire_b => onewire_b,
-- EEPROM
carrier_scl_b => carrier_scl_b,
carrier_sda_b => carrier_sda_b,
-- PCB version
pcbrev_i => pcbrev_i,
-- SPI flash
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
-- UART
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- LEDs
led_link_o => wr_led_link,
led_act_o => wr_led_act,
---------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------
plldac_sclk_o => pll20dac_sclk_o,
plldac_din_o => pll20dac_din_o,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
---------------------------------------------------------
-- SFP
---------------------------------------------------------
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
---------------------------------------------------------
-- White Rabbit
---------------------------------------------------------
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => tm_cycles,
tm_dac_value_o => tm_dac_value,
tm_dac_wr_o => tm_dac_wr_p,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en,
tm_clk_aux_locked_o => tm_clk_aux_locked,
pps_p_o => pps,
pps_led_o => pps_led,
link_ok_o => open,
---------------------------------------------------------
-- IRQ
---------------------------------------------------------
irq_user_i => irq_vector,
---------------------------------------------------------
-- FMC TDC application
---------------------------------------------------------
-- FMC EEPROM I2C
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc1_scl_b => fmc1_scl_b,
fmc1_sda_b => fmc1_sda_b,
-- FMC presence
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
fmc1_prsnt_m2c_n_i => fmc1_prsnt_m2c_n_i,
-- FMC TDC application
app_wb_o => cnx_master_out(c_WB_MASTER_VME),
app_wb_i => cnx_master_in(c_WB_MASTER_VME));
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- WISHBONE crossbar
-- 0x20000 -> TDC mezzanine SDBfmc
-- 0x10000 -> SVEC carrier UnidueID&Thermometer 1-wire
-- 0x20000 -> SVEC CSR information
-- 0x30000 -> VIC
......@@ -556,139 +585,79 @@ begin
-- 0x60000 -> TDC board on FMC#2
-- 0x80000 -> White Rabbit core
cmp_sdb_crossbar : xwb_sdb_crossbar
cmp_sdb_crossbar : xwb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
(g_num_masters => c_NUM_WB_MASTERS,
g_num_slaves => c_NUM_WB_SLAVES,
g_registered => TRUE,
g_ADDRESS => c_WB_LAYOUT_ADDR,
g_MASK => c_WB_LAYOUT_MASK)
port map
(clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
slave_i => cnx_master_out,
slave_o => cnx_master_in,
master_i => cnx_slave_out,
master_o => cnx_slave_in);
---------------------------------------------------------------------------------------------------
-- VME CORE --
---------------------------------------------------------------------------------------------------
U_VME_Core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => True,
g_USER_CSR_EXT => False,
g_WB_GRANULARITY => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_rst_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga_i,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_o => cnx_slave_in(c_MASTER_VME),
wb_i => vme_wb_in,
int_i => irq_to_vmecore);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- Drive inject also IRQ to the WB interface.
vme_wb_in.ack <= cnx_slave_out(c_MASTER_VME).ack;
vme_wb_in.err <= cnx_slave_out(c_MASTER_VME).err;
vme_wb_in.rty <= cnx_slave_out(c_MASTER_VME).rty;
vme_wb_in.stall <= cnx_slave_out(c_MASTER_VME).stall;
vme_wb_in.dat <= cnx_slave_out(c_MASTER_VME).dat;
-- VME tri-state bufferes
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
---------------------------------------------------------------------------------------------------
-- TDC BOARDS --
-- TDC BOARD 0 --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezzanine_1: fmc_tdc_wrapper
cmp_tdc_mezzanine_1: entity work.fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false )
g_SIMULATION => f_int2bool(g_SIMULATION),
g_WITH_DIRECT_READOUT => FALSE, -- true: for embedded applications, like WRTD
g_USE_DMA_READOUT => g_USE_DMA_READOUT,
g_USE_FIFO_READOUT => g_USE_FIFO_READOUT,
g_USE_FAKE_TIMESTAMPS_FOR_SIM => g_USE_FAKE_TIMESTAMPS_FOR_SIM)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => tdc1_soft_rst_n,
pll_sclk_o => tdc1_pll_sclk_o,
pll_sdi_o => tdc1_pll_sdi_o,
pll_cs_o => tdc1_pll_cs_n_o,
pll_dac_sync_o => tdc1_pll_dac_sync_n_o,
pll_sdo_i => tdc1_pll_sdo_i,
pll_status_i => tdc1_pll_status_i,
tdc_clk_125m_p_i => tdc1_125m_clk_p_i,
tdc_clk_125m_n_i => tdc1_125m_clk_n_i,
acam_refclk_p_i => tdc1_acam_refclk_p_i,
acam_refclk_n_i => tdc1_acam_refclk_n_i,
start_from_fpga_o => tdc1_start_from_fpga_o,
err_flag_i => tdc1_err_flag_i,
int_flag_i => tdc1_int_flag_i,
start_dis_o => tdc1_start_dis_o,
stop_dis_o => tdc1_stop_dis_o,
data_bus_io => tdc1_data_bus_io,
address_o => tdc1_address_o,
cs_n_o => tdc1_cs_n_o,
oe_n_o => tdc1_oe_n_o,
rd_n_o => tdc1_rd_n_o,
wr_n_o => tdc1_wr_n_o,
ef1_i => tdc1_ef1_i,
ef2_i => tdc1_ef2_i,
enable_inputs_o => tdc1_enable_inputs_o,
term_en_1_o => tdc1_term_en_1_o,
term_en_2_o => tdc1_term_en_2_o,
term_en_3_o => tdc1_term_en_3_o,
term_en_4_o => tdc1_term_en_4_o,
term_en_5_o => tdc1_term_en_5_o,
tdc_led_status_o => tdc1_led_status_o,
tdc_led_trig1_o => tdc1_led_trig1_o,
tdc_led_trig2_o => tdc1_led_trig2_o,
tdc_led_trig3_o => tdc1_led_trig3_o,
tdc_led_trig4_o => tdc1_led_trig4_o,
tdc_led_trig5_o => tdc1_led_trig5_o,
mezz_scl_i => tdc1_scl_in,
mezz_sda_i => tdc1_sda_in,
mezz_scl_o => tdc1_scl_oen,
mezz_sda_o => tdc1_sda_oen,
mezz_one_wire_b => tdc1_onewire_b,
rst_n_a_i => rst_sys_62m5_n, ------------ to be removed
fmc_id_i => '1', -- '0' for SPEC; '0' and '1' for each of the TDCs of SVEC
pll_sclk_o => fmc0_tdc_pll_sclk_o,
pll_sdi_o => fmc0_tdc_pll_sdi_o,
pll_cs_o => fmc0_tdc_pll_cs_n_o,
pll_dac_sync_o => fmc0_tdc_pll_dac_sync_o,
pll_sdo_i => fmc0_tdc_pll_sdo_i,
pll_status_i => fmc0_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc0_tdc_clk_125m_p_i,
tdc_clk_125m_n_i => fmc0_tdc_clk_125m_n_i,
acam_refclk_p_i => fmc0_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc0_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc0_tdc_start_from_fpga_o,
err_flag_i => fmc0_tdc_err_flag_i,
int_flag_i => fmc0_tdc_int_flag_i,
start_dis_o => fmc0_tdc_start_dis_o,
stop_dis_o => fmc0_tdc_stop_dis_o,
data_bus_io => fmc0_tdc_data_bus_io,
address_o => fmc0_tdc_address_o,
cs_n_o => fmc0_tdc_cs_n_o,
oe_n_o => fmc0_tdc_oe_n_o,
rd_n_o => fmc0_tdc_rd_n_o,
wr_n_o => fmc0_tdc_wr_n_o,
ef1_i => fmc0_tdc_ef1_i,
ef2_i => fmc0_tdc_ef2_i,
enable_inputs_o => fmc0_tdc_enable_inputs_o,
term_en_1_o => fmc0_tdc_term_en_1_o,
term_en_2_o => fmc0_tdc_term_en_2_o,
term_en_3_o => fmc0_tdc_term_en_3_o,
term_en_4_o => fmc0_tdc_term_en_4_o,
term_en_5_o => fmc0_tdc_term_en_5_o,
tdc_led_stat_o => fmc0_tdc_led_status_o,
tdc_led_trig_o(0) => fmc0_tdc_led_trig1_o,
tdc_led_trig_o(1) => fmc0_tdc_led_trig2_o,
tdc_led_trig_o(2) => fmc0_tdc_led_trig3_o,
tdc_led_trig_o(3) => fmc0_tdc_led_trig4_o,
tdc_led_trig_o(4) => fmc0_tdc_led_trig5_o,
mezz_scl_i => fmc0_scl_in,
mezz_sda_i => fmc0_sda_in,
mezz_scl_o => fmc0_scl_oen,
mezz_sda_o => fmc0_sda_oen,
mezz_one_wire_b => fmc0_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
......@@ -700,67 +669,76 @@ begin
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr_p(0),
slave_i => cnx_master_out(c_SLAVE_TDC0),
slave_o => cnx_master_in(c_SLAVE_TDC0),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC0_TDC),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC0_TDC),
irq_o => tdc1_irq,
clk_125m_tdc_o => tdc1_125m_clk);
irq_o => irq_vector(0),
clk_125m_tdc_o => fmc0_tdc_clk_125m);
-------------------------------------------------------------------------
fmc1_scl_b <= '0' when (fmc1_scl_oen = '0') else 'Z';
fmc1_sda_b <= '0' when (fmc1_sda_oen = '0') else 'Z';
fmc0_scl_in <= fmc0_scl_b;
fmc0_sda_in <= fmc0_sda_b;
tdc1_scl_b <= '0' when (tdc1_scl_oen = '0') else 'Z';
tdc1_sda_b <= '0' when (tdc1_sda_oen = '0') else 'Z';
tdc1_scl_in <= tdc1_scl_b;
tdc1_sda_in <= tdc1_sda_b;
cmp_tdc_mezzanine_2: fmc_tdc_wrapper
---------------------------------------------------------------------------------------------------
-- TDC BOARD 1 --
---------------------------------------------------------------------------------------------------
cmp_tdc_mezzanine_2: entity work.fmc_tdc_wrapper
generic map (
g_simulation => g_simulation,
g_with_direct_readout => false )
g_SIMULATION => f_int2bool(g_SIMULATION),
g_WITH_DIRECT_READOUT => FALSE, -- true: for embedded applications, like WRTD
g_USE_DMA_READOUT => g_USE_DMA_READOUT,
g_USE_FIFO_READOUT => TRUE,
g_USE_FAKE_TIMESTAMPS_FOR_SIM => g_USE_FAKE_TIMESTAMPS_FOR_SIM)
port map (
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => tdc2_soft_rst_n,
pll_sclk_o => tdc2_pll_sclk_o,
pll_sdi_o => tdc2_pll_sdi_o,
pll_cs_o => tdc2_pll_cs_n_o,
pll_dac_sync_o => tdc2_pll_dac_sync_n_o,
pll_sdo_i => tdc2_pll_sdo_i,
pll_status_i => tdc2_pll_status_i,
tdc_clk_125m_p_i => tdc2_125m_clk_p_i,
tdc_clk_125m_n_i => tdc2_125m_clk_n_i,
acam_refclk_p_i => tdc2_acam_refclk_p_i,
acam_refclk_n_i => tdc2_acam_refclk_n_i,
start_from_fpga_o => tdc2_start_from_fpga_o,
err_flag_i => tdc2_err_flag_i,
int_flag_i => tdc2_int_flag_i,
start_dis_o => tdc2_start_dis_o,
stop_dis_o => tdc2_stop_dis_o,
data_bus_io => tdc2_data_bus_io,
address_o => tdc2_address_o,
cs_n_o => tdc2_cs_n_o,
oe_n_o => tdc2_oe_n_o,
rd_n_o => tdc2_rd_n_o,
wr_n_o => tdc2_wr_n_o,
ef1_i => tdc2_ef1_i,
ef2_i => tdc2_ef2_i,
enable_inputs_o => tdc2_enable_inputs_o,
term_en_1_o => tdc2_term_en_1_o,
term_en_2_o => tdc2_term_en_2_o,
term_en_3_o => tdc2_term_en_3_o,
term_en_4_o => tdc2_term_en_4_o,
term_en_5_o => tdc2_term_en_5_o,
tdc_led_status_o => tdc2_led_status_o,
tdc_led_trig1_o => tdc2_led_trig1_o,
tdc_led_trig2_o => tdc2_led_trig2_o,
tdc_led_trig3_o => tdc2_led_trig3_o,
tdc_led_trig4_o => tdc2_led_trig4_o,
tdc_led_trig5_o => tdc2_led_trig5_o,
mezz_scl_i => tdc2_scl_in,
mezz_sda_i => tdc2_sda_in,
mezz_scl_o => tdc2_scl_oen,
mezz_sda_o => tdc2_sda_oen,
mezz_one_wire_b => tdc2_onewire_b,
rst_n_a_i => rst_sys_62m5_n, ------------ to be removed
fmc_id_i => '1', -- '0' for SPEC; '0' and '1' for each of the TDCs of SVEC
pll_sclk_o => fmc1_tdc_pll_sclk_o,
pll_sdi_o => fmc1_tdc_pll_sdi_o,
pll_cs_o => fmc1_tdc_pll_cs_n_o,
pll_dac_sync_o => fmc1_tdc_pll_dac_sync_o,
pll_sdo_i => fmc1_tdc_pll_sdo_i,
pll_status_i => fmc1_tdc_pll_status_i,
tdc_clk_125m_p_i => fmc1_tdc_clk_125m_p_i,
tdc_clk_125m_n_i => fmc1_tdc_clk_125m_n_i,
acam_refclk_p_i => fmc1_tdc_acam_refclk_p_i,
acam_refclk_n_i => fmc1_tdc_acam_refclk_n_i,
start_from_fpga_o => fmc1_tdc_start_from_fpga_o,
err_flag_i => fmc1_tdc_err_flag_i,
int_flag_i => fmc1_tdc_int_flag_i,
start_dis_o => fmc1_tdc_start_dis_o,
stop_dis_o => fmc1_tdc_stop_dis_o,
data_bus_io => fmc1_tdc_data_bus_io,
address_o => fmc1_tdc_address_o,
cs_n_o => fmc1_tdc_cs_n_o,
oe_n_o => fmc1_tdc_oe_n_o,
rd_n_o => fmc1_tdc_rd_n_o,
wr_n_o => fmc1_tdc_wr_n_o,
ef1_i => fmc1_tdc_ef1_i,
ef2_i => fmc1_tdc_ef2_i,
enable_inputs_o => fmc1_tdc_enable_inputs_o,
term_en_1_o => fmc1_tdc_term_en_1_o,
term_en_2_o => fmc1_tdc_term_en_2_o,
term_en_3_o => fmc1_tdc_term_en_3_o,
term_en_4_o => fmc1_tdc_term_en_4_o,
term_en_5_o => fmc1_tdc_term_en_5_o,
tdc_led_stat_o => fmc1_tdc_led_status_o,
tdc_led_trig_o(0) => fmc1_tdc_led_trig1_o,
tdc_led_trig_o(1) => fmc1_tdc_led_trig2_o,
tdc_led_trig_o(2) => fmc1_tdc_led_trig3_o,
tdc_led_trig_o(3) => fmc1_tdc_led_trig4_o,
tdc_led_trig_o(4) => fmc1_tdc_led_trig5_o,
mezz_scl_i => fmc1_scl_in,
mezz_sda_i => fmc1_sda_in,
mezz_scl_o => fmc1_scl_oen,
mezz_sda_o => fmc1_sda_oen,
mezz_one_wire_b => fmc1_onewire_b,
tm_link_up_i => tm_link_up,
tm_time_valid_i => tm_time_valid,
......@@ -772,81 +750,18 @@ begin
tm_dac_value_i => tm_dac_value,
tm_dac_wr_i => tm_dac_wr_p(1),
slave_i => cnx_master_out(c_SLAVE_TDC1),
slave_o => cnx_master_in(c_SLAVE_TDC1),
slave_i => cnx_slave_in(c_WB_SLAVE_FMC1_TDC),
slave_o => cnx_slave_out(c_WB_SLAVE_FMC1_TDC),
irq_o => tdc2_irq,
clk_125m_tdc_o => tdc2_125m_clk);
irq_o => irq_vector(1),
clk_125m_tdc_o => fmc1_tdc_clk_125m);
-------------------------------------------------------------------------
fmc1_scl_b <= '0' when (fmc1_scl_oen = '0') else 'Z';
fmc1_sda_b <= '0' when (fmc1_sda_oen = '0') else 'Z';
fmc1_scl_in <= fmc1_scl_b;
fmc1_sda_in <= fmc1_sda_b;
tdc2_scl_b <= '0' when (tdc2_scl_oen = '0') else 'Z';
tdc2_sda_b <= '0' when (tdc2_sda_oen = '0') else 'Z';
tdc2_scl_in <= tdc2_scl_b;
tdc2_sda_in <= tdc2_sda_b;
---------------------------------------------------------------------------------------------------
-- VECTOR INTERRUPTS CONTROLLER --
--------------------------------------------------------------------------------------------------
cmp_irq_vic : xwb_vic
generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 2,
g_init_vectors => c_VIC_VECTOR_TABLE)
port map
(clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => tdc1_irq,
irqs_i(1) => tdc2_irq,
irq_master_o => irq_to_vmecore);
--------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
-- Also added software resets for the clks_rsts_manager units
cmp_carrier_info : carrier_info
port map
(rst_n_i => rst_sys_62m5_n,
clk_sys_i => clk_sys_62m5,
wb_adr_i => cnx_master_out(c_SLAVE_SVEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_SLAVE_SVEC_INFO).dat,
wb_dat_o => cnx_master_in(c_SLAVE_SVEC_INFO).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_SVEC_INFO).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_SVEC_INFO).sel,
wb_stb_i => cnx_master_out(c_SLAVE_SVEC_INFO).stb,
wb_we_i => cnx_master_out(c_SLAVE_SVEC_INFO).we,
wb_ack_o => cnx_master_in(c_SLAVE_SVEC_INFO).ack,
wb_stall_o => cnx_master_in(c_SLAVE_SVEC_INFO).stall,
carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => tdc1_prsntm2c_n_i,
carrier_info_stat_p2l_pll_lck_i => '0',
-- SVEC board wrapper releases rst_sys_62m5_n only when system clock pll is
-- locked. Therefore we report here '1' - pll locked
carrier_info_stat_sys_pll_lck_i => '1',
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i(27 downto 1) => (others => '1'),
carrier_info_stat_reserved_i(0) => tdc2_prsntm2c_n_i,
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
carrier_info_ctrl_reserved_o => open,
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => carrier_info_fmc_rst); -- TDC mezzanine cores reset
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_SLAVE_SVEC_INFO).err <= '0';
cnx_master_in(c_SLAVE_SVEC_INFO).rty <= '0';
---------------------------------------------------------------------------------------------------
......@@ -873,17 +788,17 @@ begin
-- fp led number : | 5 | 6 | 7 | 8 | 1 | 2 | 3 | 4 |
-- LED 1: White Rabbit act
led_state(7 downto 6) <= c_LED_RED when wr_led_act = '1' else c_LED_OFF;
led_state(7 downto 6) <= c_LED_RED when wr_led_link = '1' else c_LED_OFF;
-- LED 2: White Rabbit link
led_state(5 downto 4) <= c_LED_GREEN when wr_led_link = '1' else c_LED_OFF;
-- LED 3: TDC1 empty flag
led_state(3 downto 2) <= c_LED_GREEN when led_tdc1_ef = '1' else c_LED_OFF;
led_state(3 downto 2) <= c_LED_GREEN when led_fmc0_tdc_ef = '1' else c_LED_OFF;
-- LED 4: TDC2 empty flag
led_state(1 downto 0) <= c_LED_GREEN when led_tdc2_ef = '1' else c_LED_OFF;
led_state(1 downto 0) <= c_LED_GREEN when led_fmc1_tdc_ef = '1' else c_LED_OFF;
-- LED 5: VME access
led_state(15 downto 14) <= c_LED_GREEN when led_vme_access = '1' else c_LED_OFF;
-- LED 6: none
led_state(13 downto 12) <= c_LED_OFF;
-- LED 6: WR PPS blink
led_state(13 downto 12) <= c_LED_GREEN when pps_led = '1' else c_LED_OFF;
-- LED 7: TDC1 locked to White Rabbit
led_state(11 downto 10) <= c_LED_GREEN when tm_clk_aux_locked(0) = '1' else c_LED_OFF;
-- LED 8: TDC2 locked to White Rabbit
......@@ -896,35 +811,51 @@ begin
port map
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => cnx_slave_in(c_MASTER_VME).cyc,
pulse_i => cnx_slave_in(c_WB_MASTER_VME).cyc,
extended_o => led_vme_access);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_drive_TDC1_EF_LED: gc_extend_pulse
cmp_drive_fmc0_tdc_EF_LED: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => tdc1_ef,
extended_o => led_tdc1_ef);
pulse_i => fmc0_tdc_ef,
extended_o => led_fmc0_tdc_ef);
-- -- -- -- -- -- --
tdc1_ef <= not(tdc1_ef1_i) or not(tdc1_ef2_i);
fmc0_tdc_ef <= not(fmc0_tdc_ef1_i) or not(fmc0_tdc_ef2_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_drive_TDC2_EF_LED: gc_extend_pulse
cmp_drive_fmc1_tdc_EF_LED: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
pulse_i => tdc2_ef,
extended_o => led_tdc2_ef);
pulse_i => fmc1_tdc_ef,
extended_o => led_fmc1_tdc_ef);
-- -- -- -- -- -- --
tdc2_ef <= not(tdc2_ef1_i) or not(tdc2_ef2_i);
fmc1_tdc_ef <= not(fmc1_tdc_ef1_i) or not(fmc1_tdc_ef2_i);
-- Div by 2 reference clock to LEMO connector
process(clk_ref_125m)
begin
if rising_edge(clk_ref_125m) then
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
-- Front panel IO configuration
fp_gpio1_b <= pps;
fp_gpio2_b <= clk_ref_div2;
fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1';
fp_gpio34_a2b_o <= '0';
end rtl;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment