... | ... | @@ -45,24 +45,22 @@ Overview of specifications of CERN developments at |
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channel](https://www.ohwr.org/project/fmc-adc-100m14b4cha) (CERN
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BE/CO) - prototype produced
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- Users
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- BPM Linac4. To be used on VME carrier (L.Soby, M.Sordet 1st
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beam end 2010)
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- BPM Linac4. To be used on VME carrier (CERN BE/BI, L.Soby,
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M.Sordet 1st beam end 2010)
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- OASIS general purpose (Deghaye)
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- PSB pick-ups, 64 cards needed on PCIe or VME (Belleman -
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BE/BI, end 2010)
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- TERA Hadron therapy, used on specific carrier with USB (N.
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Malakhov - PH/UGC, *alpha tester* June 2010)
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<!-- end list -->
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- [FmcAdc100k16b8cha: 100 kSPS, 16 bits, 8
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channel](https://www.ohwr.org/project/fmc-adc-100k16b8cha) (CERN
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BE/CO) - being designed
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- FmcAdc1/FMC2: 100 MSPS, 2 channel, 14 bit max. with auto calibration
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- (CERN BE/CO) - cancelled, replaced by
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[FmcAdc100M14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha)
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- FmcAdc2/FMC1: 1 MSPS, 8 channel, 16 bit max. (CERN BE/CO) - replaced
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by
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[FmcAdc100k16b8cha](https://www.ohwr.org/project/fmc-adc-100k16b8cha)
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<!-- end list -->
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- 128 ksps ADC (CERN TE/EPC, Q. King, G. Ramseier) - under design
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- 128 kSPS (50 kHz bandwidth) with an ADS1274 Simultaneous
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Sampling 24-Bit Delta Sigma ADC.
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... | ... | @@ -78,6 +76,17 @@ Overview of specifications of CERN developments at |
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- Will use with PCIe carrier.
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- User: TE/EPC 64 channels; SVC project (Static Var Compensators,
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11x64 signals).
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<!-- end list -->
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- 125 MSPS, 16 bits, 4 channel ADC (CERN BE/RF, J.Sanchez)
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- 50 Ohm DC-coupled, 70dBFS dynamic range, 40MHz analog bandwidth,
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gain selectable: 0dB/+24dB, thermal offset drift compensation.
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- two low jitter clock inputs and two data clock outputs.
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- *Needs carrier with HPC connector.*
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<!-- end list -->
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- 2.5 MSPS, 24-bit ADC, 1 channel, +/- 10V input, auto-calibration,
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trigger by machine timing (CERN TE/MSC, Giloteaux)
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- User: Train-B systems of AD, LEIR, PS, Booster and SPS. End 2010
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... | ... | @@ -86,13 +95,16 @@ Overview of specifications of CERN developments at |
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#### Digital to Analog Converters
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- [FMC3: 10MSPS, 4 channel, 16 bit, output range
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+/-10V.](https://www.ohwr.org/project/fmc-dac1) - Project will not
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start before 2011
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- FmcDac4ch16b125MSPS, 4 channel, 16 bit, 125 MSPS DAC
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+/-10V.](https://www.ohwr.org/project/fmc-dac1) - (CERN BE/CO),
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Project will not start before 2011
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<!-- end list -->
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- FmcDac4ch16b125MSPS, 4 channel, 16 bit, 125 MSPS DAC (CERN BE/RF,
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P.M. Leinonen), schematics ready (April 2010)
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- 40 MHz analog BW, AC-coupled, 50 Ohm, 2Vpp or 2Vpp/16 output,
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4xSMC, clock generated on MDDS mezzanine output on SMC. *Needs
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carrier with HPC connector.*
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- P.M. Leinonen (CERN BE/RF), schematics ready (April 2010)
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4xSMC, clock generated on MDDS mezzanine output on SMC.
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- *Needs carrier with HPC connector.*
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#### High-performance Time-to-Digital Converter
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... | ... | @@ -218,7 +230,7 @@ The FMC standard refers to other standards for the EEPROM data: |
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-----
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Erik van der Bij - 10 May 2010
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Erik van der Bij - 11 May 2010
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... | ... | |