... | ... | @@ -82,11 +82,14 @@ Overview of specifications of CERN developments at |
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#### High-performance Time-to-Digital Converter
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- FMC6: To be designed (CERN BE/CO) by July 2010 for TE/ABT - User:
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Carlier
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- FMC6: To be designed (CERN BE/CO) by July 2010 for TE/ABT
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- ideas: [A 17ps Time-to-Digital Converter Implemented in 65nm
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FPGA Technology, C. Favi, E.
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Charbon](http://portal.acm.org/citation.cfm?id=1508145)
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- User: E. Carlier (TE/ABT), 1 ns resolution, may use [16-channel
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TTL I/O](https://www.ohwr.org/project/fmc-dio-16chttla) for I/O)
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- User: A. Boccardi (BE/BI, Synchrotron light monitor), 50 ps
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resolution, likely another design requiring other front-end).
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#### Fine Delay module
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... | ... | @@ -171,7 +174,7 @@ The FMC standard refers to other standards for the EEPROM data: |
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- [A Brief History of FMC (VITA-57), fun
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background](http://atomicrules.blogspot.com/2009/12/brief-history-of-fmc-vita-57.html)
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\-- ErikVanDerBij - 24 March 2010
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\-- ErikVanDerBij - 25 March 2010
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