... | ... | @@ -17,14 +17,14 @@ project. |
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-----
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- [PCI Express Carrier with 1 FMC slot. Xilinx
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- [PCI Express Carrier with 1 FMC slot (LPC). Xilinx
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*Spartan*](https://www.ohwr.org/project/fmc-pci-carrier) (CERN
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BE/CO, P.Alvarez)
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- [VME FMC Carrier with 2 FMC slots. Xilinx
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- [VME FMC Carrier with 2 FMC slots (LPC). Xilinx
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*Spartan*](https://www.ohwr.org/project/fmc-vme-carrier) (CERN
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BE/BI, A.Boccardi)
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- VME FMC Carrier with 2 FMC slots. Xilinx FPGA and TI DSP (CERN
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BE/RF)
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- VME FMC Carrier with 2 FMC slots (HPC). Xilinx FPGA and TI DSP (CERN
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BE/RF, J. Molendijk)
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### FMC Mezzanines
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... | ... | @@ -43,7 +43,7 @@ Overview of specifications of CERN developments at |
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- [FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4
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channel](https://www.ohwr.org/project/fmc-adc-100m14b4cha) (CERN
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BE/CO) - prototype being built
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BE/CO) - prototype produced
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- Users
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- BPM Linac4. To be used on VME carrier (L.Soby, M.Sordet 1st
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beam end 2010)
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... | ... | @@ -90,8 +90,8 @@ Overview of specifications of CERN developments at |
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start before 2011
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- FmcDac4ch16b125MSPS, 4 channel, 16 bit, 125 MSPS DAC
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- 40 MHz analog BW, AC-coupled, 50 Ohm, 2Vpp or 2Vpp/16 output,
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4xSMC, clock generated on MDDS mezzanine output on SMC. HPC
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connector (\!)
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4xSMC, clock generated on MDDS mezzanine output on SMC. *Needs
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carrier with HPC connector.*
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- P.M. Leinonen (CERN BE/RF), schematics ready (April 2010)
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#### High-performance Time-to-Digital Converter
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