... | ... | @@ -93,7 +93,8 @@ Overview of specifications of CERN developments at |
|
|
|
|
|
<!-- end list -->
|
|
|
|
|
|
- 125 MSPS, 16 bits, 4 channel ADC (CERN BE/RF, J.Sanchez)
|
|
|
- 125 MSPS, 16 bits, 4 channel ADC (CERN BE/RF,
|
|
|
[J.Sanchez](http://consult.cern.ch/xwho/people/549249))
|
|
|
- 50 Ohm DC-coupled, 70dBFS dynamic range, ENOB ~12, 40MHz analog
|
|
|
bandwidth, +/-1V, gain selectable: 0dB/+24dB, thermal offset
|
|
|
drift compensation.
|
... | ... | @@ -155,6 +156,14 @@ Overview of specifications of CERN developments at |
|
|
- TE/ABT: Carlier
|
|
|
- CTF3: E.Said (now uses VME board)
|
|
|
|
|
|
#### Direct Digital Synthesizer
|
|
|
|
|
|
- 0-125 MHz DDS (CERN BE/RF,
|
|
|
[J.Sanchez](http://consult.cern.ch/xwho/people/549249))
|
|
|
- Generates two independent clocks, one 10 MHz reference clock
|
|
|
input
|
|
|
- *Needs carrier with HPC connector.*
|
|
|
|
|
|
-----
|
|
|
|
|
|
## FPGA Mezzanine Card (FMC) standard info
|
... | ... | |