Erik van der Bij · 816998cc
--- a/Home.md
+++ b/Home.md
 # Project description:
-*This project is cancelled. The [simple PCIe FMC
+**This project is cancelled. The [simple PCIe FMC
-carrier](https://www.ohwr.org/project/spec) is similar.***
+carrier](https://www.ohwr.org/project/spec) is similar.**
 The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an
 SFP connector. On the PCIe side it has a 4-lane interface, while the FMC
@@ -23,42 +23,35 @@ Projects](https://www.ohwr.org/project/fmc-projects).
 *Main Features**
-\* 4-lane PCIe bus (Gennum GN4124)  
+- 4-lane PCIe bus (Gennum GN4124)  
-\* FMC slot  
+- FMC slot  
-o 1 full LPC slot  
+  - 1 full LPC slot  
-o DP1 to DP4 gigabit links of HPC  
+  - DP1 to DP4 gigabit links of HPC  
-o CLK2\_BIDIR and CLK3\_BIDIR only from carrier to mezzanine  
+  - CLK2\_BIDIR and CLK3\_BIDIR only from carrier to mezzanine  
-o +5V, -2V, -5V2 and -12V optionally wired on HPC pins  
+  - +5V, -2V, -5V2 and -12V optionally wired on HPC pins  
-\* 1 Spartan6 FPGA, XC6SLX150T-2FGG676C  
+- 1 Spartan6 FPGA, XC6SLX150T-2FGG676C  
-\* Flexible clocking resources  
+- Flexible clocking resources  
-o 2 Voltage Controlled Temperature Compensated Crystal Oscillator
+  - 2 Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO)  
-(VCTCXO)  
+  - 1 any rate I2C programmable crystal oscillator (Si570)  
-o 1 any rate I2C programmable crystal oscillator (Si570)  
+  - 1 Direct Digital Synthesizer (DDS) (AD9910)  
-o 1 Direct Digital Synthesizer (DDS) (AD9910)  
+  - 2 Phase Locked Loop (PLL) chips for clock cleaning and redistribution to the FPGAs and the pluggable modules (AD9516-4)  
-o 2 Phase Locked Loop (PLL) chips for clock cleaning and redistribution
+- On board memory  
-to the FPGAs and the pluggable modules (AD9516-4)  
+  - 72Mbit QDR-II SRAM (CY7C1512KV18-250BZXC)  
-\* On board memory  
+  - A 2Gbit DDR3 (MT41J128M16HA-15E)  
-o 72Mbit QDR-II SRAM (CY7C1512KV18-250BZXC)  
+  - 1 SPI 128Mbit flash proms for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data  
-o A 2Gbit DDR3 (MT41J128M16HA-15E)  
+- Front panel connectivity  
-o 1 SPI 128Mbit flash proms for multiboot FPGA powerup configuration,
+  - Small Formfactor Pluggable (SFP) fibre-optic connector  
-storage of the FPGA firmware or of critical data  
+- Internal connectors  
-\* Front panel connectivity  
+  - 2 e-SATA connected to 2 GTP blocks  
-o 1 Small Formfactor Pluggable (SFP) fibre-optic connector  
+  - 1 e-SATA connected to 1 AD9516-4 LVDS output and 1 FPGA differential IO.  
-\* Internal connectors  
+  -  1 e-SATA connected to a AD9516-4 CLK\_IN and to an FPGA GCLK, and 1 FPGA differential IO.  
-o 2 e-SATA connected to 2 GTP blocks  
+  - 1 JTAG header  
-o 1 e-SATA connected to 1 AD9516-4 LVDS output and 1 FPGA differential
+- FPGA configuration. The FPGA can optionally be programmed from:  
-IO.  
+  - JTAG header  
-o 1 e-SATA connected to a AD9516-4 CLK\_IN and to an FPGA GCLK, and 1
+  - GN4124 GPIO  
-FPGA differential IO.  
+  - SPI EEPROM or GN4124 SPRIO interface (selected with optional 0Ohm resistors)  
-o 1 JTAG header  
+- 12-layer PCB  
-\* FPGA configuration. The FPGA can optionally be programmed from:  
+- [White Rabbit](https://www.ohwr.org/project/white-rabbit) will be supported by the FMC Standard Kit carriers.
-o JTAG header  
-o GN4124 GPIO  
-o SPI EEPROM or GN4124 SPRIO interface (selected with optional 0Ohm
-resistors)  
-\* 12-layer PCB  
-\* [White Rabbit](https://www.ohwr.org/project/white-rabbit) will be
-supported by the FMC Standard Kit carriers.
 -----
@@ -74,20 +67,14 @@ supported by the FMC Standard Kit carriers.
      - [Controls EDMS
        page](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCFEIB___:V0/TAB4)
-[Reference
+- [Reference
 design](https://www.ohwr.org/project/fmc-pci-carrier/uploads/c8c0242dfa73144c8f747524081a9ddd/pfc_reference_design.tar.gz)
+- [Functional Specifications](FunctionalSpec)
-[Functional Specifications](FunctionalSpec)
+- [Technical Specifications](TechSpec)
+- [Clocking guidelines](https://www.ohwr.org/project/fmc-pci-carrier/wikis/Documents/Clocking-recomendations-for-FMCs-and-Spartan6)
-[Technical Specifications](TechSpec)
+- [Planning](Planning)
+- [Configuration-Options](Configuration-Options)
-[Clocking guidelines](https://www.ohwr.org/project/fmc-pci-carrier/wikis/Documents/Clocking-recomendations-for-FMCs-and-Spartan6)
+- [Debug tools and utilities](DebugTools)
-[Planning](Planning)
-[Configuration-Options](Configuration-Options)
-[Debug tools and utilities](DebugTools)
 -----
@@ -100,10 +87,7 @@ design](https://www.ohwr.org/project/fmc-pci-carrier/uploads/c8c0242dfa73144c8f7
 |19-05-2010|Mechanics of front-panel designed, 3 prototypes will be built.|
 |26-05-2010|Schematics review planned to be held on 2 June. Gennum engineer will also review. [Schematics review files](SchReview)|
 |28-05-2010|First placement of components on board. A full-sized PCIe card will be used.|
-|03-06-2010|Review of schematics. Simplified power scheme and reduced number of different components.
+|03-06-2010|Review of schematics. Simplified power scheme and reduced number of different components. Board will be shorter so that it can fit in more slots of the industrial PCs we use. Suggestion came up to make a very [simple PCIe FMC carrier](https://www.ohwr.org/project/spec) having only the necessary for standard cards (ADC, DAC, Fine delay, TDC etc.).|
-Board will be shorter so that it can fit in more slots of the industrial PCs we use.
-Suggestion came up to make a very [simple PCIe FMC carrier](https://www.ohwr.org/project/spec) having only the necessary
-for standard cards (ADC, DAC, Fine delay, TDC etc.).|
 |05-08-2010|PCB layout review held. [review03082010](review03082010)|
 |08-09-2010|PCB modifications ready. Waiting for a final check.|
 |13-09-2010|PCB modifications before production. [review13092010](review13092010)|
@@ -114,8 +98,7 @@ for standard cards (ADC, DAC, Fine delay, TDC etc.).|
 |25-11-2010|Received PCIe front-panels. Issue with size of cutouts.|
 |10-12-2010|PCIe communication to registers in Xilinx working.|
 |03-02-2011|First DMA transfer to/from DDR3 memory.|
-|04-05-2011|QDR memory access working with non-open core written by the company Eurotel.
+|04-05-2011|QDR memory access working with non-open core written by the company Eurotel. Needs improvement as the qdr_a and qdr_d signals are placed at two different sides of the device.|
-Needs improvement as the qdr_a and qdr_d signals are placed at two different sides of the device.|
 |04-05-2011|The project is actually on hold. The [simple PCIe FMC carrier](https://www.ohwr.org/project/spec) is similar.|
 |11-06-2014|Project cancelled. It will never be built again.|