Implement TRST in nanoFIP JTAG master
For the next gateware release nanoFIP could benefit from adding TRST to its master JTAG implementation.
On the mezzanine, TRST should be connected to the FMC connector pin h17 (LA11_N), currently GPIO0. It is GCA1/IO69PDB1 pin of the nanoFIP FPGA.