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AIDA-2020 TLU
Commit 791171bd authored by Alvaro Dosil's avatar Alvaro Dosil
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ucf files to test the v1 and v1a boards using sp605

parent de762276
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firmware/hdl/test/sp605_FMC_mTLU.ucf 0 → 100644
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NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=C18;
NET dip_switch_i<1> LOC=Y6;
NET dip_switch_i<2> LOC=W6;
NET dip_switch_i<3> LOC=E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger inputs
# first constant-fraction-discrimiator comparator outputs
NET "CFD_DISCR_P_I<0>" LOC = "G9"; ## "FMC_LA00_CC_P" , G6 on FMC
NET "CFD_DISCR_N_I<0>" LOC = "F10"; ## "FMC_LA00_CC_N" , G7 on FMC
NET "CFD_DISCR_P_I<1>" LOC = "C17"; ## "FMC_LA14_P" , C18 on FMC
NET "CFD_DISCR_N_I<1>" LOC = "A17"; ## "FMC_LA14_N" , C19 on FMC
NET "CFD_DISCR_P_I<2>" LOC = "H13"; ## "FMC_LA12_P" , C22 on FMC
NET "CFD_DISCR_N_I<2>" LOC = "G13"; ## "FMC_LA12_N" , C23 on FMC
NET "CFD_DISCR_P_I<3>" LOC = "C5"; ## "FMC_LA16_P" , C26 on FMC
NET "CFD_DISCR_N_I<3>" LOC = "A5"; ## "FMC_LA16_N" , C27 on FMC
#NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
# then threshold comparator outputs
# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
NET "output_0_p[0]" LOC = H10;
NET "output_0_p[1]" LOC = W17;
NET "output_0_p[2]" LOC = F7;
NET "output_0_n[0]" LOC = H11;
NET "output_0_n[1]" LOC = Y18;
NET "output_0_n[2]" LOC = F8;
NET "output_1_p[0]" LOC = U16;
NET "output_1_p[1]" LOC = V11;
NET "output_1_p[2]" LOC = C19;
NET "output_1_n[0]" LOC = V15;
NET "output_1_n[1]" LOC = W11;
NET "output_1_n[2]" LOC = A19;
NET "output_2_p[0]" LOC = Y17;
NET "output_2_p[1]" LOC = AA14;
NET "output_2_p[2]" LOC = B20;
NET "output_2_n[0]" LOC = AB17;
NET "output_2_n[1]" LOC = AB14;
NET "output_2_n[2]" LOC = A20;
NET "output_3_p[0]" LOC = D4;
NET "output_3_p[1]" LOC = AA16;
NET "output_3_p[2]" LOC = B2;
NET "output_3_n[0]" LOC = D5;
NET "output_3_n[1]" LOC = AB16;
NET "output_3_n[2]" LOC = A2;
\ No newline at end of file
firmware/hdl/test/sp605_FMC_mTLU_v1a.ucf 0 → 100644
View file @ 791171bd
NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=C18;
NET dip_switch_i<1> LOC=Y6;
NET dip_switch_i<2> LOC=W6;
NET dip_switch_i<3> LOC=E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
#
# I/O to devices under test
#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger inputs
# first constant-fraction-discrimiator comparator outputs
#NET "CFD_DISCR_P_I<0>" LOC = "W17"; ## "FMC_LA00_CC_P" , G6 on FMC
#NET "CFD_DISCR_N_I<0>" LOC = "Y18"; ## "FMC_LA00_CC_N" , G7 on FMC
#NET "CFD_DISCR_P_I<1>" LOC = "Y15"; ## "FMC_LA14_P" , C18 on FMC
#NET "CFD_DISCR_N_I<1>" LOC = "AB15"; ## "FMC_LA14_N" , C19 on FMC
#NET "CFD_DISCR_P_I<2>" LOC = "AA16"; ## "FMC_LA12_P" , C22 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "AB16"; ## "FMC_LA12_N" , C23 on FMC
#NET "CFD_DISCR_P_I<3>" LOC = "AA14"; ## "FMC_LA16_P" , C26 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "AB14"; ## "FMC_LA16_N" , C27 on FMC
##NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
##NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
##NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
##NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
# then threshold comparator outputs
# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
NET "output_0_p[0]" LOC = R9;
NET "output_0_p[1]" LOC = B18;
NET "output_0_p[2]" LOC = C5;
NET "output_0_n[0]" LOC = R8;
NET "output_0_n[1]" LOC = A18;
NET "output_0_n[2]" LOC = A5;
NET "output_1_p[0]" LOC = AA10;
NET "output_1_p[1]" LOC = G8;
NET "output_1_p[2]" LOC = V11;
NET "output_1_n[0]" LOC = AB10;
NET "output_1_n[1]" LOC = F9;
NET "output_1_n[2]" LOC = W11;
NET "output_2_p[0]" LOC = V7;
NET "output_2_p[1]" LOC = T12;
NET "output_2_p[2]" LOC = B2;
NET "output_2_n[0]" LOC = W8;
NET "output_2_n[1]" LOC = U12;
NET "output_2_n[2]" LOC = A2;
NET "output_3_p[0]" LOC = R11;
NET "output_3_p[1]" LOC = C17;
NET "output_3_p[2]" LOC = H13;
NET "output_3_n[0]" LOC = T11;
NET "output_3_n[1]" LOC = A17;
NET "output_3_n[2]" LOC = G13;
\ No newline at end of file
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