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AIDA-2020 TLU
Commit 53f07c9a authored by Alvaro Dosil's avatar Alvaro Dosil
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Showing with 14 additions and 13 deletions
firmware/hdl/common/dualSERDES_1to4_rtl.vhd
View file @ 53f07c9a
......@@ -97,9 +97,9 @@ BEGIN
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", --"VARIABLE_FROM_HALF_MAX",
IDELAY_VALUE => 116,--116, -- Amount of taps for fixed input delay (0-255)
SIM_TAPDELAY_VALUE=> 10 -- Per tap delay used for simulation in ps
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
IDELAY_VALUE => 0 -- Amount of taps for fixed input delay (0-255)
--SIM_TAPDELAY_VALUE=> 10 -- Per tap delay used for simulation in ps
)
port map (
-- BUSY => s_busy_idelay_m, -- 1-bit output: Busy output after CAL
......@@ -129,11 +129,10 @@ BEGIN
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", --"VARIABLE_FROM_ZERO",
IDELAY_VALUE => 150,--130, -- Amount of taps for fixed input delay (0-255)
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
SIM_TAPDELAY_VALUE => 10 -- Per tap delay used for simulation in ps
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
IDELAY2_VALUE => 0 -- Delay value when IDELAY_MODE="PCI" (0-255)
--SIM_TAPDELAY_VALUE => 10 -- Per tap delay used for simulation in ps
)
port map (
-- BUSY => s_busy_idelay_s, -- 1-bit output: Busy output after CAL
......
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @ 53f07c9a
......@@ -34,7 +34,7 @@ ENTITY top_extphy IS
sysclk_p_i : IN std_logic;
threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
reset_i : IN std_logic;
reset_i : IN std_logic;
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
......@@ -42,8 +42,8 @@ ENTITY top_extphy IS
gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
leds_o : OUT std_logic_vector (3 DOWNTO 0);
phy_rstb_o : OUT std_logic;
dut_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
dut_clk_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
......@@ -171,9 +171,10 @@ ARCHITECTURE struct OF top_extphy IS
trigger_i : IN std_logic ; -- goes high when trigger logic issues a trigger
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
reset_or_clk_to_dut_i : IN std_logic ; -- ! Either reset line or trigger
handshake : IN std_logic_vector(3 downto 0); -- handshake enabled
ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
......@@ -425,6 +426,7 @@ BEGIN
clk_to_dut_i => s_DUT_clk,
trigger_i => s_Trig_TO_DUT, --overall_trigger,
reset_or_clk_to_dut_i => s_rst_or_clk_to_dut,
handshake => x"0", -- Handshake selected
ipbus_o => ipbr(0),
clk_to_dut_n_o => dut_clk_n_o,
clk_to_dut_p_o => dut_clk_p_o,
......
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