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AIDA-2020 TLU
Commit 43b1584c authored by Alvaro Dosil's avatar Alvaro Dosil
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firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
View file @ 43b1584c
......@@ -34,6 +34,7 @@ ENTITY top_extphy IS
sysclk_p_i : IN std_logic;
threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
reset_i : IN std_logic;
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
......@@ -287,8 +288,8 @@ ARCHITECTURE struct OF top_extphy IS
ipbus_o : OUT ipb_rbus ;
strobe_16x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
extclk_p_b : OUT std_logic ; -- either external clock in, or a clock being driven out
extclk_n_b : OUT std_logic ;
extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
extclk_n_b : INOUT std_logic ;
DUT_clk_o : OUT std_logic ;
logic_clocks_locked_o : OUT std_logic ;
logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
......@@ -305,6 +306,7 @@ ARCHITECTURE struct OF top_extphy IS
strobe_4x_logic_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
reset_i : IN std_logic;
trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); -- ! Copy of input trigger level. High bits CFD, Low threshold
......@@ -346,8 +348,7 @@ ARCHITECTURE struct OF top_extphy IS
g_IPBUS_WIDTH : positive := 32
);
PORT(
clk_4x_logic_i : IN std_logic;
DUT_clk_i : IN std_logic;
clk_i : IN std_logic;
Trigger_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
......@@ -404,7 +405,7 @@ BEGIN
shutter_cnt_i <= (OTHERS => '0');
-- ModuleWare code(v1.12) for instance 'I8' of 'sor'
overall_veto <= buffer_full_o OR veto_o;
overall_veto <= '0';--buffer_full_o OR veto_o;
-- Instance port mappings.
I0 : DUTInterfaces
......@@ -553,9 +554,10 @@ BEGIN
strobe_4x_logic_i => strobe_4x_logic,
threshold_discr_p_i => threshold_discr_p_i,
threshold_discr_n_i => threshold_discr_n_i,
reset_i => reset_i,
trigger_times_o => trigger_times,
trigger_o => triggers,
trigger_debug_o => gpio_hdr,
trigger_debug_o => gpio_hdr,
edge_rising_times_o => OPEN,
edge_falling_times_o => OPEN,
edge_rising_o => OPEN,
......@@ -593,8 +595,7 @@ BEGIN
g_IPBUS_WIDTH => g_IPBUS_WIDTH
)
PORT MAP(
clk_4x_logic_i => clk_4x_logic,
DUT_clk_i => s_DUT_clk,
clk_i => s_DUT_clk,
Trigger_i => overall_trigger,
ipbus_clk_i => ipbus_clk,
ipbus_i => ipbw(10),
......
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