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AIDA-2020 TLU
Commit 030b71ff authored by Alvaro Dosil's avatar Alvaro Dosil
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Interface prepared to change I/O clock for the old TLU handshake

parent a4d29208
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Showing with 56 additions and 12 deletions
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ 030b71ff
......@@ -70,14 +70,16 @@ ENTITY DUTInterfaces IS
trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
clk_to_dut_i : IN std_logic ; -- ! clock to DUT
reset_or_clk_to_dut_i : IN std_logic;
handshake : IN std_logic_vector(3 downto 0); -- handshake enabled
ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
clk_to_dut_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
veto_o : OUT std_logic -- goes high when one or more DUT are busy
veto_o : OUT std_logic; -- goes high when one or more DUT are busy
clk_to_tlu_o : OUT std_logic
);
-- Declarations
......@@ -92,6 +94,8 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_strobe_4x_logic_d1 : std_logic;
signal s_clk_to_DUT , s_busy_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0);
signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
signal s_clk_is_output, s_clk_is_output_b : std_logic := '0'; --! Indicates the direction of the clock in the RJ45 DUT
signal s_clk_to_tlu : std_logic := '0';
constant c_N_CTRL : positive := 1;
constant c_N_STAT : positive := 1;
......@@ -149,6 +153,55 @@ BEGIN
s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
-- These instances need to be out of the loop because the RJ45 permits a bidirectional clock
clk_to_DUT_OBUFDS_inst_0 : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(0), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(0), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(0) -- Buffer output
);
clk_to_DUT_OBUFDS_inst_1 : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(1), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(1), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(1) -- Buffer output
);
clk_to_DUT_OBUFDS_inst_2 : IOBUFDS
generic map (
IOSTANDARD => "BLVDS_25")
port map (
O => s_clk_to_tlu, -- Buffer output
IO => clk_to_dut_p_o(2), -- Diff_p inout (connect directly to top-level port)
IOB => clk_to_dut_n_o(2), -- Diff_n inout (connect directly to top-level port)
I => s_clk_to_dut(2), -- Buffer input
T => s_clk_is_output_b -- 3-state enable input, high=input, low=output
);
s_clk_is_output <= '1' when handshake = x"0" else
'0';
--When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
--also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
--output.
ddr_for_clk_to_DUT_tristate : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => s_clk_is_output_b, -- 1-bit output data
C0 => clk_to_dut_i, -- 1-bit clock input
C1 => not clk_to_dut_i, --not s_clk160_internal, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => s_clk_is_output, -- 1-bit data input (associated with C0)
D1 => '0', --not s_clk_is_xtal, -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
duts: for dut in 1 to g_NUM_DUTS generate
busy_IBUFDS_inst : IBUFDS
......@@ -162,15 +215,6 @@ BEGIN
IB => busy_from_dut_n_i(dut-1) -- Diff_n buffer input (connect directly to top-level port)
);
clk_to_DUT_OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
OB => clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
I => s_clk_to_dut(dut-1) -- Buffer output
);
trig_OBUFDS_inst : OBUFDS
generic map (
......
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