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David Cussans authored
- changed IPBus read from FIFO in eventBuffer_rtl.vhd. Probably uncessary, but not going back now. In process changed FIFO to standard rather than fall-through and decreased size ( to try to help with timing closure ) - Put SHREG attribute in logic_clocks_rtl.vhd. Should also add to other places. - Added pulse stretch to stretchPulse_rtl.vhd ( used to be just delay ) - Randomly hacked event formatter until it records which trigger fired. - trigger logic hacked to provide only a single clock cycle trigger ( rather than staying high for however long the trigger combination was active. - Trying to reduce timing errors by specifying which nets don't need timing closure ( using TIG ) in sp605_FMC_mTLU_v1a.ucf - Uncommented re-generate IP in build_bitstream.tcl
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