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# AIDA FMC TLU
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## Overview
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A Trigger/Timing Logic Unit designed for use with High Energy Physics
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beam-tests. Provides a simple and flexible interface for fast timing and
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triggering signals at the AIDA pixel sensor beam-telescope. Implemented
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as a double-width FMC with single LPC connector. Compatible with EUDET
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JRA1 TLU.
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( A prototype, the mini-TLU is described HERE
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)
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![](/uploads/b76cc7d66ebafa9def5fe8097ef832f8/tlu_front_and_top.png)
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## Specification
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Parameter</strong></td>
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<td><strong>Value</strong></td>
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</tr>
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<tr class="even">
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<td>Number of trigger inputs (scintillator, NIM , TTL)</td>
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<td>6</td>
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</tr>
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<tr class="odd">
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<td>Trigger discriminator type</td>
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<td>One Threshold, one CFD per input</td>
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</tr>
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<tr class="even">
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<td>Trigger input voltage range</td>
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<td>± 5V max.</td>
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</tr>
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<tr class="odd">
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<td>Trigger input connector type</td>
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<td>Lemo single-pole size-00</td>
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</tr>
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<tr class="even">
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<td>Trigger input termination</td>
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<td>50 Ohm.</td>
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</tr>
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<tr class="odd">
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<td>Trigger threshold range</td>
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<td>± 1.3V software controlled</td>
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</tr>
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<tr class="even">
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<td>Trigger threshold accuracy</td>
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<td>± 5mV</td>
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</tr>
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<tr class="odd">
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<td>Number of clock I/O</td>
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<td>1</td>
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</tr>
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<tr class="even">
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<td>Clock I/O connector type</td>
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<td>Lemo two-pole size-00</td>
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</tr>
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<tr class="odd">
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<td>Clock I/O voltage levels</td>
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<td>LVDS</td>
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</tr>
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<tr class="even">
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<td>Clock I/O termination</td>
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<td>100 Ohm differential, if used as an input</td>
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</tr>
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<tr class="odd">
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<td>Number of connectors for "Devices Under Test" (DUT)</td>
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<td>4</td>
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</tr>
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<tr class="even">
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<td>DUT connector type</td>
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<td>HDMI</td>
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</tr>
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<tr class="odd">
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<td>Number of signals per DUT</td>
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<td>5</td>
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</tr>
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<tr class="even">
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<td>DUT voltage levels</td>
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<td>LVDS</td>
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</tr>
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<tr class="odd">
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<td>DUT signal termination</td>
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<td>100 Ohm differential for inputs</td>
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</tr>
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</tbody>
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</table>
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-----
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## Hardware
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The database files for the schematic capture ( Cadence HDL ) and PCB
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layout ( Cadence Allegro ) are available in the project Subversion
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respository: http://svn.ohwr.org/fmc-mtlu/trunk/circuit_board
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A circuit schematic in PDF format is available here:
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http://svn.ohwr.org/fmc-mtlu/trunk/circuit_board/Schematics/fmc_tlu_v1a.pdf
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-----
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## Firmware
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The TLU communicates over a Gigabit serial link using the IPBus
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protocol: https://svnweb.cern.ch/trac/cactus/wiki ,
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https://ipbus.web.cern.ch/ipbus/
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A description of the firmware (produced by Doxygen from comments in the
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code) is found here:
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http://svn.ohwr.org/fmc-mtlu/trunk/documents/firmware/doxygen/output/html/index.html
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Instructions on building the firmware are found here:
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[FirmwareBuild-FMC-TLU](FirmwareBuild-FMC-TLU)
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Details of how to simulate the firmware are found here:
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[SimulationEnvironment-FMC-TLU](SimulationEnvironment-FMC-TLU)
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-----
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## Software
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For testing purposes the TLU can be controlled/read-out using Python
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scripts using the PyChips or uHAL libraries. These scripts can be found
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here:
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http://svn.ohwr.org/fmc-mtlu/trunk/firmware/scripts . One of the scripts
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startTLU.py allows time-stamp data to be read out and stored in a Root
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file. [startTLU-instructions](startTLU-instructions)
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The TLU is fully integrated into the EUDAQ framework ( see:
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http://eudaq.hepforge.org/ ).
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-----
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## Network
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The TLU communicates with a host-PC over Gigabit/s Ethernet using the
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IPBus protocol layered on top of UDP/IP.
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With the current firmware version the IP address of the TLU FPGA is set
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to 192.168.200.30 . In a future release it will be possible to change
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this by programming an on-board PROM
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\---
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## Testing hardware
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Details of how to test the miniTLU hardware, and test results from
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existing miniTLUs can be found here:
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[Hardware-Testing](Hardware-Testing)
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-----
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## Project Documents
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A short "User Manual" for the mini-TLU is available here:
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http://svn.ohwr.org/fmc-mtlu/trunk/documents/firmware/latex/AIDA_TLU_note.pdf
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-----
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## Interface to CALICE Timing System ( CCC )
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The AIDA-2020 TLU can interface to the Clock and Control Card of the
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CALICE Calorimetry development project. Details can be found here:
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[TLU-to-CCC-Interface](TLU-to-CCC-Interface)
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-----
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## Reporting Problems
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Use the bug-tracker to report bug/problems/suggestions :
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https://www.ohwr.org/work_packages/new
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Monitor existing issues here:
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https://www.ohwr.org/project/fmc-mtlu/issues
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-----
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## Status
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| **Date**| \* Event \*|
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| 10-Feb-2011 | Creation of AIDA Mini-TLU project in OHWR. |
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| 18-Feb-2011 | AIDA Kick-off meeting at CERN. Initial specification of
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mTLU |
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| March-2013 | First prototype version of TLU available for tests|
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| January-2014 | Second prototype version of TLU available for tests|
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| May-2016 | Schematic capture started on third prototype |
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| June-2016 | Schematic for third prototype ready for review|
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-----
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## Useful References
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- [Description of the JRA1 Trigger Logic Unit (TLU),
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v0.2c](http://www.eudet.org/e26/e28/e42441/e57298/EUDET-MEMO-2009-04.pdf)
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, EUDET-Memo-2009-4
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<!-- end list -->
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- [Talks/posters](Talks/posters) ( at meeting, conferences )
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-----
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David Cussans - 10 February 2014
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